MPC5777C-Parallell accesses through EBI

[MatheusFranklin]

Hello!

I am working with a MPC5777C in dual core configuration. While measuring the hardware resource contention interference in timing, my teammate noticed a 40% increase in task execution time when both cores were acessing the EVB's external SDRAM through the EBI. The on-chip SRAM has two Platform RAM Controllers that allow parallel memory acessess, atenuating inter-core interference when each controller is allocated to different cores. I know that the MPC5777C does not have two EBIs, but is there a way to decrease intercore interference coming from the EBI?

Best regards, 

Matheus

[MatheusFranklin]

Hello!

In my understanding, your solution will not atenuate shared resources competition impact on timing. It will just define which core will take more interference by "losing" the resource competition more times (i.e., having lower access priority). In the example that I mentioned, the on-chip SRAM has two Platform Memory Controllers that could be allocated individually for each core. This configuration leads to lower interference because I would be dedicating independent controllers to individual cores.

I was expecting for the EBI somethig like using 16 bits of the bus for one core and 16 bits for other. I just need to make 16 bits access to the EBI, so if it could be possible, would work for me.

Best regards

[davidtosenovjan · Accepted solution]

It is expected to use internal SRAM memory (internal SRAM is split into two halves according address line 18 (see Table 9-2. XBAR slave port assignments). It can be beneficial if one core accesses slave port 2 and second core accesses slave port 4 (or otherwise) as both accesses goes in parallel.

You can split EBI data bus to two 16-bit halves, but it does not help as it will be sequential access anyway. There is only one dedicated XBAR slave port for EBI module what means only one master can access EBI at a time.

[MatheusFranklin]

This answers my question. Thank you, David!

[davidtosenovjan]

SDRAM cannot be connected to the EBI module, I suppose you mean SRAM.

Pay attention to XBAR priority, choosing of round-robin arbitration scheme would solve this issue and both cores would have equal chance to access the slave. Or you may set up fixed priority to define higher priority for one core over other (or other master).

[MatheusFranklin]

Hello!

I think I did not use the correct reply button previously, so I believe you did not receive a notification. Sorry for that. Could you evaluate the previous reply that I made, please?

Best regards,
Matheus