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Contributor III


Could i ask for some help with investigation of an exception? We are using MPC5777C and S32 Design Studio IDE.
After execution of function FLASH_DRV_Program we get an exception IVOR1. The issue can be reproduced every time and it happens in bootloader during flashing of application with iso-tp/uds always at the same address. The exception registers are as follows:

SRR0= 0x800068C8; //SPR 26
SRR1= 0x02009000; //SPR 27
CSRR0= 0x00000000; //SPR 58
CSRR1= 0x00000000; //SPR 59
DEAR= 0x00000000; //SPR 61
ESR= 0x00000000; //SPR 62
IVPR= 0x80000000; //SPR 63
IVOR0= 0x00000400; //SPR 400
IVOR1= 0x00000410; //SPR 401
IVOR2= 0x00000420; //SPR 402
IVOR3= 0x00000430; //SPR 403
IVOR4= 0x00000440; //SPR 404
IVOR5= 0x00000450; //SPR 405
IVOR6= 0x00000460; //SPR 406
IVOR7= 0x00000470; //SPR 407
IVOR8= 0x00000480; //SPR 408
IVOR9= 0x00000490; //SPR 409
IVOR10= 0x000004A0; //SPR 410
IVOR11= 0x000004B0; //SPR 411
IVOR12= 0x000004C0; //SPR 412
IVOR13= 0x000004D0; //SPR 413
IVOR14= 0x000004E0; //SPR 414
IVOR15= 0x000004F0; //SPR 415
IVOR32= 0x00003EB0; //SPR 528
IVOR33= 0x0000FAD0; //SPR 529
IVOR34= 0x00001A00; //SPR 530
IVOR35= 0x0000EFF0; //SPR 531
MCSRR0= 0x80000410; //SPR 570
MCSRR1= 0x00000000; //SPR 571
MCSR= 0x08090000; //SPR 572
MCAR= 0x00020410; //SPR 573
DSRR0= 0x73F65C5C; //SPR 574
DSRR1= 0x5B615BF3; //SPR 575

MCSR register has bits set: IF (Instruction Fetch Error), MAV (MCAR Address Valid) and EXCP_ERR (ISI, TLB or Bus Error on first instruction fetch for an exception handler). According to the core reference manual because MEA is 0 it would limit the reasons to only ISI or Bus Error. The address in MCAR points to the ivor1Vector.

According to core reference manual:
Instruction Storage interrupt (ISI) which is also IVOR3 occurs when no higher priority exception exists and an Execute Access Control exception occurs. This interrupt is implemented as defined by PowerISA 2.06.,with the addition of Misaligned Instruction Fetch exceptions, and the extension of the Byte Ordering exception status to also cover Mismatched Instruction Storage exceptions.

Am i correct in understanding that an IVOR3 could be masked by IVOR1 because it is a higher prio exception? Would SRR0 indicate address for IVOR3 exception in this case?

What is a bus error exactly?

What are the root-causes for ISI and Bus error and how can they be prevented? How can i investigate this further? Any help would be greatly appreciated.

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3 Replies

NXP TechSupport
NXP TechSupport

I am sure if “masking” is the right word.


In case it happen situation IVOR3 is supposed to be invoked and IVOR3 handler is unreadable to some reason (misconfigured, pointing to invalid memory and so), IVOR1 is called.


IVOR1 (machine check) does not touch SRR0/1 thus their content should be unaltered (i.e. it may be by IVOR3 if it have happened).


Bus error means in general data/instruction cannot be read/written/executed. It aggregates all possible cause including ECC errors, unreadable memories, reading from reserves spaces,  and similar. For specific cause it is needed to evaluate MCSR register.

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Contributor III


Thank you for your response. So what is the exception reason in this case? IVOR1 couldn't happen because IVOR1 handler instruction couldn't be executed. There had to be initial reason for IVOR1. The bits in MCSR indicate several possibilities. How to identify which one it is that caused this exception? The addresses for ivor handlers are IVOR1: 0x00020410 (physical) / 0x80020410 (virtual) and IVOR3 0x00020430 (physical) / 0x80020430 (virtual) so they should be valid.

Best regards

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NXP TechSupport
NXP TechSupport

Have you checked MMU/MPU setting? Does have mentioned virtual address range set access right properly?

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