MPC5777C , FlexCAN, ESR1 to clear into ISR

[mauriziogreco]

Hi all.

I m working on MPC5777c . Into ISR for managing interrupt event related to errors (for example absence of ACK) I'm found this strange problem.

Into the ISR I try to clear the ESR1 register with this approach.

_ISR2( FlexCAN_A_Error )
{
..... /* Instruction....of ISR  not reported*/

/* Reset interrupt flag */
CAN_A.ESR1.R = 0x00000002;
}

Using lauterbach I found that after execution of  CAN_A.ESR1.R = 0x00000002 the bit related to ERRINT it remains at 1.

What I'm doing in wrong way?

Thanks all for a possible suggest to solve the problem.

Regards.

[mauriziogreco]

Hi, I solved my self.

Problem was related to absence of ACK. Also if ISR clean the CAN_A.ESR1.R bit related to error, other CAN messages (already present in some messages box) are try to send messages re-generating bit setting into CANA.ESR1.R.

Solution for me is the "aborting" tx of all pending message box if the rate of continous irq (in absence of ACK) is dangerous for sw execution!

[alexandrunan]

Hello Maurizio,

Be aware that reading ESR1 reqister will automatically clear next errors: BIT1ERR,
BIT0ERR, ACKERR, CRCERR, FRMERR, and STFERR. TXWRN, RXWRN, IDLE,
TX, FLTCONF, and RX. And if you continue hitting interrupt that means an ongoing transmission it's more causing the problem. You can check the bus status before trying to send.