MPC5777C EQADC configuration

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MPC5777C EQADC configuration

1,417 Views
vrushalitaklika
Contributor III

Hi, I am trying to initalise EQADC0 in MPC5777C controller.

How do I configure EQADC.CFPR register with below configuration

/* Send CFIFO 0 a ADC0 configuration command */
/* enable ADC0 & sets prescaler= divide by 10 */

In the datasheet EQADC.CFPR register does not have register bitwise e4xplanation.

Can someone help on configuraing CFPR register.

Thanks

Vrushali

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11 Replies

231 Views
vrushalitaklika
Contributor III

Hi,

I have a confusion on using CFPR and RFPR register.

How to decide when to use CFPR[0] CFPR[1] CFPR[2]... and same for RFPR[0]. RFPR[1].

Here is my implementation is this correct

EQADC_A.CFPR[0].R = 0x00000000 | (ANA12_TO_ADC_IA1<<8) ;
EQADC_A.CFPR[0].R = 0x00100000 | (ANA21_TO_ADC_DCLINK1_LK<<8) ;
EQADC_A.CFPR[0].R = 0x80200000 | (ANA6_TO_ADC_DCLINK1_V<<8) ;
EQADC_A.CFPR[1].R = 0x00000000 | (ANA34_TO_ADC_INV1_TA <<8) | (1 << 24); //1 is calibration value
EQADC_A.CFPR[1].R = 0x00100000 | (ANA35_TO_ADC_INV1_TB <<8) | (1 << 24); //1 is calibration value
EQADC_A.CFPR[1].R = 0x00200000 | (ANA36_TO_ADC_INV1_TD <<8) | (1 << 24); //1 is calibration value
EQADC_A.CFPR[1].R = 0x80300000 | (ANA37_TO_ADC_INV1_TC <<8) | (1 << 24); //1 is calibration value

Thanks

Vrushali

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231 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

CFPRx/RFPRx chooses particular Command/Result FIFO number. Lower FIFO number has higher priority when priority processing is necessary.

pastedImage_1.png

Choosing of FIFO is completely up to you.

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231 Views
vrushalitaklika
Contributor III

Thanks David.

I have 10 analog channels to convert, and we have 6 RFIFO, can you suggest how can we convert all 10 channels in one function itself.

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231 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Also you could pay attention to short bulletin I have written:

https://community.nxp.com/docs/DOC-329779 

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231 Views
vrushalitaklika
Contributor III

Hi David,

Do you have example of document eQADC - avoiding unintended result swap  ?

Have you implemented the solutions? I am looking for 4th solution proposed

4) To keep regular alternating of commands assigned to ADC0 and ADC1.

Thanks

Vrushali

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231 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

How I said it is completely application dependent. If you only need to convert 10 channels in sequence, you can just use only CFIFO0 and RFIFO0, for instance.

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231 Views
vrushalitaklika
Contributor III

Thanks David

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230 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

It is register for writing commands to CFIFO either due to conversion command in standard or alternate configuration or for indirect access to On-Chip ADC registers.

pastedImage_1.png

I could recommend you to see following example codes:

Example MPC5674F eQADC+eDMA Single_Scan CW210 

Example MPC5674F eQADC+eDMA Continuous_Scan CW210 

Example MPC5644A eQADC channel 146 conversion+calibration CW210 

Also I am attaching header file that could be possibly useful for you.

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vrushalitaklika
Contributor III

Hi David, do you have a C file where you have used this eqadc_mamcros_Mamba.h file

Thanks

Vrushali

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230 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

I have used it in this example:

Example MPC5674F eQADC-Streaming Mode CW210 

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vrushalitaklika
Contributor III

Thanks David.

I implemented same way.

However my requirement is, I have to use

22 channels of EQADCA and 7 channels of EQADC B

How do I modular the code so that for every channel configuration same function is called always.

Also need clarification when to use CFPR[0] and CFPR[1]  etc and likewise CFCR0 and CRFR1 registers etc.

Here is my init and send and receive functions.

void eqadc_init (struct EQADC_tag *my_eqadc)
{
/* CBuffer0 */

my_eqadc->CFPR[0].R = B0 | MESSAGE_TAG(NULL_M) | LST(CYCLES_2) | CHANNEL(4);
my_eqadc->CFPR[0].R = EOQ | B1 | MESSAGE_TAG(NULL_M) | LST(CYCLES_2) | CHANNEL(4);

/*Trigger CFIFO 0 using Single Scan SW mode */
my_eqadc->CFCR0.R= SINGLE_SCAN_ENABLE | MODEx(SOFTWARE_TRIGGER_SINGLE_SCAN);

/*Wait for End Of Queue flag*/
while(my_eqadc->FISR[0].B.EOQFX != 1) {}
my_eqadc->FISR[0].R = End_of_Queue_Flag;


}

void SendConvCmd(struct EQADC_tag *my_eqadc, int channelnum)
{
/* Conversion command: convert channel 5 */
/* with ADC0, set EOQ */
my_eqadc->CFPR[0].R = EOQ | channelnum<<8;
}

void ReadResult(struct EQADC_tag *my_eqadc, int *Result)
{
while(my_eqadc->FISR[0].B.RFDFX != 1){}; /* Wait for RFIFO 0's Drain Flag to set */
Result = my_eqadc->RFPR[0].R; /* ADC result */
//ResultInMv = (vuint32_t)((5000*Result)/0x3FFC);
my_eqadc->FISR[0].R = RFIFO_Drain_Flag; /* Clear RFIFO 0's Drain Flag */

}

From main function I am calling it as below

eqadc_init(&EQADC_A);
eqadc_init(&EQADC_B);


SendConvCmd(&EQADC_A, 4); // here 4 corresponds to channel no 4
ReadResult(&EQADC_A, &duty);

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