MPC5777C EBI external memory access

[prathapvc]

We have configured EBI to access external memory devices in our application as below

a)  External SRAM - CS0 - 0x20000000 - 0x20FFFFFF

b)  RTRAM memory- CS1 - 0x21000000 - 0x21FFFFFF

The following signals from MPC5777C are connected to 

a)  External SRAM -

1. Address Lines 9-30

2. Data Lines 0-15

3. RD_WR 

4. Chip Select 0 (CS0)

5. Output Enable (OE)

b) RTRAM memory -

1. Address Lines 10-30

2. Data Lines 0-15

3. RD_WR 

4. Chip Select 1 (CS1)

But OE — Output Enable (OE) pin from EBI is not connected to RTRAM memory device and after accessing External SRAM memory we are not able to access RTRAM memory. So since OE — Output Enable (OE) pin from EBI is not connected to RTRAM memory device, can this lead to any EBI bus contention issue. Also can we set Output Enable (OE) pin to default state after accessing External SRAM memory.

[davidtosenovjan]

Hi, I would not assume it as OE signal is connected to external SRAM. Have you tried some larger write/read sequence to mentioned RTRAM? To be honest I have never seen a memory connected without OE signal, I would say it is necessary.

What is your cache configuration? Just wondering whether in you non-faulty configuration you aren't just accessing cache memory instead of the target.

Have you measured with logic analyzer?

You said in previous threads that SRAM access block subsequent accesses to other memories. Could you show me SRAM scheme of connection?

[prathapvc]

Hi David,

Yes as per my earlier threads SRAM access blocked subsequent accesses to RTRAM and we found out that the only difference is OE signal from MPC5777C is not connected to RTRAM but connected to SRAM. Please find the attached file of SRAM schematic

[davidtosenovjan]

Could you show also EBI signals on MCU side? Specifically I am interested to know how you have connected address pins. I.e. which pin fits to signal APL1ADDR0, for instance.

Do you have it connected according EBI FAQs, section 4?

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/External-Bus-Interface-FAQs/ta-p/1124068

[prathapvc]

Hi David,

Please see attached file of address pins connection at MCU and from MCU side address lines are going to buffers where ADD9 -ADD30 lines are flipped (like ADD9 corresponds to ADDR30, ADD10 corresponds to ADDR29, similarly other address lines are also flipped) and then connected to external SRAM.

[davidtosenovjan]

Then it seems to be correct.

You could try to to configure EBI_BR[GCSN]=1 if don't have it so what's affect back-to-back accesses adding one dead cycle between negation of one CS and assertion of another.

Otherwise I would consult missing OE line with RTRAM memory manufacturer.

[prathapvc]

Hi David

What is the default cache configuration for SRAM access? Also how to ensure in non-faulty configuration cache memory is not accessed.