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MPC5777C Core1 Boot process

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MPC5777C Core1 Boot process

‎12-10-2020 03:54 AM
1,038 Views
darq
Contributor III

Hello,

I'm trying to start core 1 on SPC5777C. What i found in the documentation is that i should set the reset vector for core 1 in SIU.RSTVEC1 and reset bit SIU.HLT1.CORE1. What should be the reset vector exactly?

I set it to the address of _start function in startup.s of bootloader common for both cores. The issue that i'm facing is that i get exception Ivor13 when the startup code in startup.s is trying to disable SWTs due to i assume not configured MMU for core 1. Core 0 MMU is configured by BAM but core 1 does not execute BAM? Configuration of MMU is disabled in startup.s by preprocessor define but even if it is enabled there are other exceptions after configuring first entry of MMU (see attached screen). What should be the boot procedure for core 1? 

core1_exception.png

 P.S.: Why is S32 Design Studio showing different content for EmbSys Registers? Shouldn't those be shared between cores?

Thank you for you help

 

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‎12-14-2020 03:33 AM
1,014 Views
darq
Contributor III

Hello,

Ok, i seem to have found the solution. As long as i do not change the SIU.RSTVEC1, by default core 1 starts at the address of BAM. Then BAM, after setting up MMU, jumps to the default start address of 0x0080 0000 which is what i wanted. Still not sure why there were exceptions though.

In our implementation since core 1 is started from inside of main function of application, there is no way that core 0 and core 1 can access the same startup source code at the same time (they are in completely different flash sectors). 

Yes, EmbSys registers is just a name of microcontroller registers in S32 like SIU, eMIOS, PMC etc. For some reason they have different content for both cores.

Best regards

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‎12-10-2020 11:24 PM
1,026 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

@darq wrote:

I'm trying to start core 1 on SPC5777C. What i found in the documentation is that i should set the reset vector for core 1 in SIU.RSTVEC1 and reset bit SIU.HLT1.CORE1. What should be the reset vector exactly?

The reset vector is the address where the core1 will start execution. Usually it is start address of core1 startup code.

@darq wrote:

I set it to the address of _start function in startup.s of bootloader common for both cores. The issue that i'm facing is that i get exception Ivor13 when the startup code in startup.s is trying to disable SWTs due to i assume not configured MMU for core 1. Core 0 MMU is configured by BAM but core 1 does not execute BAM? Configuration of MMU is disabled in startup.s by preprocessor define but even if it is enabled there are other exceptions after configuring first entry of MMU (see attached screen). What should be the boot procedure for core 1? 

Hmm, you should have separate startup for core1. Or you can simply use address of core1 main. If you set same address for both cores then one of your core won't be able to access the memory as it is occupied by other. And you will also execute same instruction 2x once the memory is released by core0. This is not correct approach.

@darq wrote:

 P.S.: Why is S32 Design Studio showing different content for EmbSys Registers? Shouldn't those be shared between cores?

Hmm, what is EmbSys registers. There are no such registers on this device. Is it some GUI naming in S32? Sorry I use mostly GHS compiler with Trace32.

best regards,

Peter

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