martinkovar
Hi Martin,
As you suggested in the last response, i made changes and tried the polling way,
1.The transfer from master is working good.
Reason: I checked using a DSPI SR status register,as shown in the code.
2.But the slave receive buffer is still reading 0(zero).
Doubt:
1. As the master is successfully transferring the data out,will that prove Master clock is generating good?
Code:
int main(void)
{
HW_Init();
SPI2_Init(); //master
SPI1_Init(); //slave
/* Initialize MASTER DSPI_2 response to Slave,with EOQ */
/*WIth the status register EOQ, used to check the transfer of data from master*/
DSPI_2.PUSHR.PUSHR.R = 0x08015678; //EOQ is enabled
/* Transmit data from slave SPI to master */
DSPI_1.PUSHR.PUSHR.R = 0x00001234;
while(DSPI_2.SR.B.EOQF == 0); //Checking for EOQ flag, which is passing.
RecDataSlave = DSPI_1.POPR.R; //Reading slave receive buffer - which reads 0(zero), checked using GDB debugger.
RecDataMaster = DSPI_2.POPR.R; //Reading the master receive buffer.
DSPI_0.SR.R = 0xFCFE0000; //clearing slave status register
DSPI_2.SR.R = 0xFCFE0000; //Clearing Master status register.
}
Hardware Connection:
Pins Master (DSPI_2) Slave(DSPI_1)
CS (PL[11]) <------------------------------------- > PH[14]
SCK PL[14] <-----------------------------------------> PF[5]
SIN - SOUT (SIN)PL[13] <------------------------------------------>PM[10](SOUT)
SOUT-SIN (SOUT)PL[12]<----------------------------------------->PF[4](SIN)
GPIO Initialization:
static void GPIO_Init(void)
{
/*Master GPIO Configuration, DSPI_2*/
SIUL2.MSCR_IO[187].R = 0x32840003; //DSPI2_CS2 PL[11] which is declared low in DSPI_MCR to start comm.
SIUL2.MSCR_IO[190].R = 0x32840003; //DSPI2_SCK PL[14]
SIUL2.MSCR_IO[188].R = 0x32840003; //DSPI2_SOUT PL[12]
SIUL2.MSCR_IO[189].R = 0x308C0000; //DSPI0_SIN
SIUL2.MSCR_MUX[374].B.SSS = 0x8; //DSPI0_SIN
/*Slave GPIO Configuration, DSPI_1*/
SIUL2.MSCR_IO[126].R = 0x308C0003; //DSPI1_CS0 PH[14]
SIUL2.MSCR_IO[85].R = 0x308C0000; //DSPI1_SCK PF[5]
SIUL2.MSCR_MUX[372].B.SSS = 0x1; //884-512 = 372
SIUL2.MSCR_IO[84].R = 0x308C0000; //DSPI1_SIN PF[4]
SIUL2.MSCR_MUX[371].B.SSS = 0x3;
SIUL2.MSCR_IO[202].R = 0x32840004; //DSPI1_SOUT PM[10]
}
Kindly review and let us know your suggestions and corrections to be made on the issue.
Regards
Sandeep Nagarajan