I have been trying to use atomic Compare-and-Store DMSC instruction, but it gives machine check exception. Not able to with BUS_DRERR, MAV, G and LD set in MCSR. The address range is accessible (other DMSC operations are working I tried Load-and-set-1 (bit)). Here is the code that I am using:
e_lis r5, 0x9000 ; Create decoration: cast.h, CD16 0
lhdcbx r4, r5, r3 ; Atomic set resource, caching inhibited
se_cmpi r4, 0x0
se_blr ; Return
Help shall be appreciated.
the decoration information in r5 is not correct. It's not valid opcode, so machine check is triggered. You can find in the reference manual:
If I use opcode 0x6.... instead of 0x9..., the instruction is executed successfully.