MPC5748G: What is the correct address of MC_CGM_AC5_SC?

[alexvinchev]

If using MPC5748G.h revision 1, address of the mentioned register is 0xFFFF 08A0.

If using MPC5748G.h revision 3, address of the mentioned register is 0xFFFF 01C0. This is the address, specified in the actual RM (MPC5748G Reference Manual, Rev. 3 , 04/2014)

According to the statement here: Re: MPC5748G: What is the purpose of PLLDIG.PLLCAL3 register (not present in MPC5748GRM) and how to ... up to date revision of header file is revision 3, where address corresponds to the actual RM.

When I'm using MPC5748G.h revision 3 and trying to run PLL from the "Fast external crystal osc. (FXOSC)", MCU stays at "Fast Internal crystal osc. (FIRC)" clock, i.e. I'm unable to use FXOSC.

When I'm using MPC5748G.h revision 1, clock is changed from FIRC to FXOSC.

[petervlna · Accepted solution]

Hi,

When I am looking at header file, the MC_CGM [AC5_SC] is located at 0xFFFB01C0 and not at 0xFFFF 01C.

#define MC_CGM (*(volatile struct MC_CGM_tag *) 0xFFFB0000UL)

But to answer you quesiton. The reason is simple.

On cut 1 device the MC_CGM[AC5_SC] is located on address 0xFFFB_08A0

On cut 2 device the MC_CGM[AC5_SC] is located on address 0xFFFB_01C0

So if you are using the cut2 or newer use the header file ver3 or later. For cut 1 use the olde header file revision.

Bye,

Peter

[alexvinchev]

OK petervlna​,

Maybe it's a dumb question, but what do you mean by "cut 1", "cut 2", etc?

I have two types of devices:

On the right side is the one, which came with the MPC574XG-MB + MPC574XG-256DS evaluation set.

On the left side is one of the bunch of chips, we ordered and received separately. Looking externally, I can assume that one on the left is newer than one on the right.

If I look at the Freescale web site, I can order now only PPC5748GK1MMJ6A...

If I take JTAGID (p.3248 of RM) value is 0x0988001D, which gives: PRN = 0, DC = 0x26, PIN = 0x80 (instead of 0x81 as specified on the rev.3 RM), MIC = 0x00E.

Same number for both devices above.

I can understand changing of register address on different devices from same MCU family, but changing those on different die revisions is totally new and quite surprising for me.

Is there a deterministic way to tell which device I have and which device I will receive in the future. I hope that memory mapping will not change with each die revision, otherwise I have to manage specific software for each die revision, which is a kind of insanity...

[petervlna]

Hi,

You have old device which is cut 1.

Key:

0N65H - Cut 1

1N81M - Cut 2

Yes, there is a difference on MC_CGM mapping.

To prevent any issues I suggest you to do development on cut2. As all revision released in future will be based on cut2.

In future you will not be able to order cut1 devices as they will be obsolete if they are not obsolete now.

Not talking about fixes done on Cut2.

Bye,

Peter

[alexvinchev]

Sorry, 0xFFFFxxxx was typing mistake, because I'm developing on separate machine.