MPC5748G FlexCAN configuration (non CANFD usage)

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MPC5748G FlexCAN configuration (non CANFD usage)

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alexvinchev
Contributor V

Hi,

I need strong advice regarding FlexCAN configuration. Preferably from someone, experienced in configuring such module.

I have read thoroughly reference manual in FlexCAN part (Chapter 43), but I cannot bet that I've understood it at 100%, counting that there are many possible different configurations. I've also made some tests and few different configurations.

It seems I have no problem with transmission, but I have huge problems with reception.

 

My use case is the following:

1. MB0 - MB3 are used for transmission (either standard ID and/or extended ID frames).

2. MB4-MB63 (CUT0) or MB4-MB95(CUT1) are used for reception (either standard ID and/or extended ID frames). Idea is to catch ALL incoming frames, regardless of their ID or type - standard or extended.

3. RXFIFO should NOT be used.

 

Questions:

1. Is it possible to configure FlexCAN to achieve this behavior?

2. How I should configure mask/id pairs in order to receive any message on the CAN network (first message goes to the first MB in RX EMPTY state)? It is allowable to receive STD ID frames to (let say) MB4-MB15 and EXT ID to MB16-MB63/MB95.

3. Is it possible to use global masking in this scenario, or there should be individual masking for each MB?

 

Best regards,

Aleksandar

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) Yes, it is possible.

2) You can just set a mask acceptance register(s) properly, means clear all bits. In that case the received ID is “don’t care”. If you want to receive both standard and extended frames then at least 2 MBs should be set for receive, one for standard (IDE=0) and other for extended frames (IDE=1).

For your config you can set MB4-MB15 for STD ID and MB16-MB63/MB95 for EXT ID. But the question could be if you need so many RX MBs. Maybe you want to create some reception queue.

3) You can use both the global and individual masking. But if doing reception queue, global masking will not help a lot.

- When global masking is used the MCR[IRMQ] is cleared. In that case the matching winner is the first matched MB regardless if it is free-to-receive or not. Thus the message is always stored in the first MB.

- If individual masking is used (MCR[IRMQ]=1) the matching winner is selected according to the priority below:

  1. the first free-to-receive matched MB;
  2. the last non free-to-receive matched MB.

The MB is “free-to-receive” if

- The CODE field of the Mailbox is EMPTY

- The CODE field of the Mailbox is either FULL or OVERRUN and it has already been serviced (the C/S word was read by the CPU and unlocked).

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) Yes, it is possible.

2) You can just set a mask acceptance register(s) properly, means clear all bits. In that case the received ID is “don’t care”. If you want to receive both standard and extended frames then at least 2 MBs should be set for receive, one for standard (IDE=0) and other for extended frames (IDE=1).

For your config you can set MB4-MB15 for STD ID and MB16-MB63/MB95 for EXT ID. But the question could be if you need so many RX MBs. Maybe you want to create some reception queue.

3) You can use both the global and individual masking. But if doing reception queue, global masking will not help a lot.

- When global masking is used the MCR[IRMQ] is cleared. In that case the matching winner is the first matched MB regardless if it is free-to-receive or not. Thus the message is always stored in the first MB.

- If individual masking is used (MCR[IRMQ]=1) the matching winner is selected according to the priority below:

  1. the first free-to-receive matched MB;
  2. the last non free-to-receive matched MB.

The MB is “free-to-receive” if

- The CODE field of the Mailbox is EMPTY

- The CODE field of the Mailbox is either FULL or OVERRUN and it has already been serviced (the C/S word was read by the CPU and unlocked).

BR, Petr

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alexvinchev
Contributor V

Hi,

I'm finally done with the tests. You're completely right about the configuration. Unfortunately, this was my initial configuration.

I have very unusual behavior when EXT ID is in use in mixed STD/EXT ID environment. There is interrupt for each frame received, but when MB is read it is empty or garbage. Then I stop execution through the debugger and start it again (delay < 1s, no other actions). This stop completely changes the behavior of the MCU. Starting from this moment, both STD and EXT ID frames are received correctly unless CAN controller is re-initialized. Really weird behavior. If you know what is going on, you can write here. If not, you can skip investigation, since today I have direct support from NXP FAE and I hope that problem will be solved faster with him.

Thank you for your effort!

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alexvinchev
Contributor V

Thank you for the advice,

I'll test again tomorrow and will respond back.

Reason to post my questions was that in previous tests in extended mode not all messages were received...

If I properly understood, with mask set to 0 the ID field will be "not care", so I could skip setting MB ID field...

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PetrS
NXP TechSupport
NXP TechSupport

Yes, with mask registers set to 0 the ID field is “not care” so you can skip the MB ID field setting. Anyway the ID field is updated with the received one, so each time can be different. You should just set the IDE bit to distinguish between standard and extended frames.