MPC5748G 2 cores reading from the same address.

[MattJCole]

I know you cannot have two cores writing to the same memory address at the same time without there being a problem, but can two cores read from the same memory address at the same time?  

[MatthewCole]

I have shared section of RAM that is used between the cores. The cores will never write to the same location of RAM at the same time but the both can try to read the same location of RAM at the same time. Also, one core can write to the location of RAM will the other core is reading. What would happen? Also do you have an example of how to use XBAR.

[petervlna]

Hello,

Also, one core can write to the location of RAM will the other core is reading. What would happen?

That depends on settings of exceptions. Usually the core will finish write and then will release slave on XBAR (PRAM). Second core will read RAM ASAP the slot on XBAR for RAM (slave) is ready.

Also do you have an example of how to use XBAR.

Not sure what kind of example you are referring to. XBAR is HW bus with configurable access priorities.

All the details are in reference manual Chapter 16 Crossbar Switch (AXBS)

Best regards,

Peter

[MatthewCole]

I want to make sure if I understand what will happen. It sounds like only one core can access a location in RAM at a time. Once one core is done the other core is given access to the location in RAM. I just want to make sure there is no way an exception can be thrown (program to crash) that will cause a watch dog to reset the processor.

[petervlna]

Hello,

When a master (your core0 or core1) accesses the crossbar switch, the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the
requesting master simply sees wait states inserted until the targeted slave port can service
the master's request. The latency in servicing the request depends on each master's
priority level and the responding slave's access time.

From HW standpoint you will wait until the slave slot is free. No exception will be triggered from this process.

If your master is not able to enter memory where the watchdog handler is located and you will get an exception from watchdog... that is something different and need to be taken care of on SW level.

Best regards

[petervlna]

Hello,

can two cores read from the same memory address at the same time?

No. Please refer to XBAR for example. 1 master can access 1 slave at the time.

Best regards,

Peter