MPC5746R-252DS borderline design (VDD_LV_CORE)

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MPC5746R-252DS borderline design (VDD_LV_CORE)

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jamesmurray
Contributor V

Seems that as supplied, the power supply capacitance design on the MPC5746R 252 daughtercard is borderline.

Test procedure - set the board to use the MB 1.25_SR as the source for the core:

Daughterboard:

J19 = open

J17 = open

J18 = 1-5

MPC57XXMB Motherboard:

J60 = open

#1

Power up.

Processor boots ok.

#2 Now replace the J18 shunt with a length of wire, say 70mm long.

Power up.

Processor is stuck in reset.

PORST is off. Scoping the RESET line shows a 50% duty 121Hz signal.

#3

Add a 4.7u capacitor between TP16 and TP18

Power up.

Processor boots ok.

The schem shows a number of non-pop 4.7u caps on VDD_LV_CORE - why ? I suggest these be populated in future builds.

Test #2 is similar to using a off-board 1.25 regulator.

regards

James

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

Hmm, usually the EVB boards are made with great reserve in case of design.

I will try to get feedback from application engineer.

regards,
Peter

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jamesmurray
Contributor V

Any news ?

James

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jamesmurray
Contributor V

Any news?

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718 Views
petervlna
NXP TechSupport
NXP TechSupport

Hi,

I have sent your questions to application engineer.

But up to now I didn't get any response.

I do not expect that he will unless this is entered as ticket to our system trough web site.

Since I am general support I am not able to answer all technical details for HW.

I suggest you to write official ticket on nxp.com, or try to contact the sales/ FAE assigned to your company or distributor to speed this up.

regards,

Peter

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jamesmurray
Contributor V

Thanks for your reply. I have created a case no. 00264903

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