MPC5746C DMA+SPI when set &&SPI_0.PUSHR.PUSHR.R generates an DBE error

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MPC5746C DMA+SPI when set &&SPI_0.PUSHR.PUSHR.R generates an DBE error

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weiq
Contributor I

MPC5746C  DMA+SPI when set &&SPI_0.PUSHR.PUSHR.R generates an DBE error ie.The last recorded error was a bus error on a destination write.but if Destination address is array,the transport is right

Below is the configuration process:

first:channel link

DMAMUX_0.CHCFG[15].B.SOURCE = 12; //spi0 TX
DMAMUX_0.CHCFG[15].B.TRIG = 0;
DMAMUX_0.CHCFG[15].B.ENBL = 1;

second:set TCD

MCU_IO_DMA_Disable(DMANumber);
DMA.TCD[DMANumber].SADDR.B.SADDR = (UINT32)&DMA_TEST_ARR[0];  // Start Address
DMA.TCD[DMANumber].DADDR.B.DADDR = (UINT32)&SPI_0.PUSHR.PUSHR.R;  // Destination address
DMA.TCD[DMANumber].ATTR.B.SMOD = 0; // Source address modulo
DMA.TCD[DMANumber].ATTR.B.DMOD = 0x00; // Destination address modulo
DMA.TCD[DMANumber].ATTR.B.DSIZE = 0x02; // Destination transfer size : 32 Bits
DMA.TCD[DMANumber].ATTR.B.SSIZE = 0x02; // Source transfer size : 32 Bits
if(Send)
{
DMA.TCD[DMANumber].SOFF.B.SOFF = 4 ; // Signed source address offset
//DMA.TCD[DMANumber].NBYTES.MLOFFYES.B.DMLOE = 1 ; // Inner "minor" byte count
//DMA.TCD[DMANumber].NBYTES.MLOFFYES.B.MLOFF = 1 ; // Inner "minor" byte count
DMA.TCD[DMANumber].NBYTES.MLNO.B.NBYTES = 4 ; // Inner "minor" byte count
//DMA.TCD[DMANumber].NBYTES.MLOFFYES.B.SMLOE = 1 ; // Inner "minor" byte count
DMA.TCD[DMANumber].SLAST.B.SLAST = -(QueueSize*4); // last Signed source address adjust
DMA.TCD[DMANumber].DOFF.B.DOFF = 0x0; // Signed destination address offset
DMA.TCD[DMANumber].DLASTSGA.B.DLASTSGA = 0; // Signed destination address adjust

DMA.TCD[DMANumber].BITER.ELINKNO.B.ELINK = 0x0; // //Channel-to-channel Linking on Minor Loop Complete
DMA.TCD[DMANumber].BITER.ELINKNO.B.BITER = 4; // begining "major" iteration count
DMA.TCD[DMANumber].CITER.ELINKNO.B.ELINK = 0x0; // Channel-to-channel Linking on Minor Loop Complete
DMA.TCD[DMANumber].CITER.ELINKNO.B.CITER=4; // Current ¡°major¡± iteration count Disabled
DMA.TCD[DMANumber].CSR.B.BWC = 0x2; // Bandwidth control : No DMA Stalls
DMA.TCD[DMANumber].CSR.B.MAJORLINKCH = 0x00; // Major Channel number
DMA.TCD[DMANumber].CSR.B.MAJORELINK = 0x0; // Major Channel Link : Disabled
DMA.TCD[DMANumber].CSR.B.DONE = 0x00; // Channel Done
DMA.TCD[DMANumber].CSR.B.ACTIVE = 0x00; // Channel ACtive
DMA.TCD[DMANumber].CSR.B.ESG = 0x0; // Enable Scatter/Gather : Disabled
DMA.TCD[DMANumber].CSR.B.DREQ = ExecOnce; // Do NOT disable TCD When done
DMA.TCD[DMANumber].CSR.B.INTHALF = 0x0; // Interrupt on minor loop count
DMA.TCD[DMANumber].CSR.B.INTMAJOR = 0x0; // Interrupt on major loop completion : Disabled
DMA.TCD[DMANumber].CSR.B.START = 0x00; // Explicit Channel Start bit
MCU_IO_DMA_Enable(DMANumber);
}

DMA.TCD[15].CSR.B.START = 0x01;

捕获.PNG

DBE error what mean,but if Destination address is array,the transport is right

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

did you setup access rights for Masters and Peripherals on AIPS?

For DMA and SPI0 you can use this...

 

AIPS_A.MPRA.R |= 0x7000; // enable DMA to go through AIPS_A
AIPS_A.OPACR[1].R = 0x0; // SPI0 has no protection

BR, Petr