Hi,
there will be some changes in next RM revision, refer to below pictures. From this there could be 2 options:
- 50MHz generated by PHY, then PG8 serves as RMII_CLK input and Aux Clock Sel10 must be configured to select this for ENET_CLK
- 50MHz generated internally and output on PG8. Aux Clock Sel10 configured for internal source (e.g PLL0), RCCR[RMII_CLK_EN] bit set (presently GCR register). PG8 connected to PHY clock input.
BR, Petr