Hi,
I am new to this processor and I have a few questions about its pins during reset/configuration.
I read in the reference manual that the state of the WKPCFG pin is sampled during processor reset and the state of that pin determines how the eTPU and eMIOS pins are pulled (up/down) during reset.
1. Is there a way to specify each pins pull up/down setting independently. If so, how?
2. Can the pins be tri-stated?
3. Can the pins pull up/down configuration be changed after reset or is it always the same after reset as during reset?
4. Where are the answers to these questions in the processor documentation?
Thanks!
Nick
Hi,
1. No.
2. No, only pull-up or pull-down can be selected on eTPU and eMIOS pins as a default state during reset and after reset.
3. After reset, you can reconfigure the pins as needed. See the SIU.PCR[n] register.
4. I think that "Table 2-4. Signal Properties..." in reference manual and description in SIU chapter is clear enough. The table shows state during reset and default state after reset for all GPIO pins and it makes sense that the default settings can be reconfigured.
Regards,
Lukas
Lukas,
I was looking at table 3-22 and it seems like there is a register for most pins. So I cannot program each register independently to control the pull up down configuration?
Nick
Reset state and default state after reset is given. All you can do is to change state of eMIOS and eTPU pins by WKPCFG pin.
Once the device is up and running (i.e. out of reset), you can configure each single pin individually accordingly to your needs. Once the reset is asserted again, reset state of all pins is applied again.
Lukas
Lukas,
Thank you for your feedback. I looked at the SIU_PCR register and it has a bit field for setting a pin as an open drain. Does this setting take effect during reset as well or only after reset is over?
Nick