MPC5675K / eTimer configuration

[adelos]

Hi,

We're working on frequency acquisition with eTimer peripheral of MPC5675K. We got some issue to properly configure it. The RM isn't well documented about input capture mode and how the capture FIFO works. (how to manually empty the FIFO for example), No application notes, No examples.

Anyone had an idea how to "proper" configure the eTimer peripheral for frequency/duty cyle acquisition ? had details about the role of CFWM (Capture FIFO Water Mark) and it's impact on FIFO management ?

Thx

Adel.

[adelos]

Hi,

Lukas and Petr, thanks for your quick support and for the example.

Regards,

Adel.

[PetrS · Accepted solution]

Hi,

see attached example. It gives possible implementation of input signal period/freq measurement.

eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter value on rising/falling edge of input signal. The FIFO is set

to 2 entries and ICF2 is monitored. Free-running mode is used here.

eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter.

BR,

Petr

[matthewclark]

Is there a version of this that works under CW MCU 10.4 SE?  I tried copying the uart.c and uart.h files into a basic "Hello World" type of program for my MPC5675_EVB and it dies with the following error in uart.h.

#if !_MSL_CONSOLE_SUPPORT

#error _MSL_CONSOLE_SUPPORT must not be defined to 1.

#endif

I chased things down to ansi_params.h which had the following:

#if defined(_No_Console) && !defined(_MSL_CONSOLE_SUPPORT)

#define _MSL_CONSOLE_SUPPORT 0

#endif

But I've no idea where in the CW210 project these things are defined.  It seems like it should be a simple thing to do in MCU 10.4, but can anyone show me the light?

Matt

[PetrS]

Hi Matt,

this should be defined in [CW2.x_installation]\PowerPC_EABI_Support\MSL\MSL_C\MSL_Common\Include\ansi_parms.h

In the Eclipse version see [CW10.x_installation]\MCU\PA_Support\ewl\EWL_C\include\ansi_parms.h

I think it is enough to change _MSL_CONSOLE_SUPPORT to _EWL_CONSOLE_SUPPORT in your uart.h.

Hope it helps.

BR,

Petr

[lukaszadrapa]

The CAPTn register is actually the 2-deep FIFO. It means that the capture logic is able to save up to 2 counter values for each capture circuit. Once a FIFO is full the FIFO is needed to read out to be able to accept new values. The FIFO watermark determines when the ICFn flag is set (0..single capture, 1.. 2 captures). The FIFO is read out by repetitive reads of CAPTn register.

I will attach example at the start of next week.

Lukas