MPC5675K(PXS3020) EBI Configuration

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MPC5675K(PXS3020) EBI Configuration

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mohammedshibin
Contributor I

Hai all,

 

I am using a PXS3020(473 pinout) controller for a project. I am trying to interface external memory through EBI.

 

I am  using all the four chip selects and the details are given below.

 

1.) CS0 is connected to flash memory(2 MB) - No clock out, No burst memory access, 55 ns access time

 

2.) CS1 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time

 

3.) CS2 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time

 

4.) CS3 is connected to FPGA memory(256 KB)

 

 

 

The register configuration that I did is given below.

 

EBI_MCR - 0x0000_0005(No external master, 16 bit data port, using 16 to 31 as data line, No multiplexed address and data lines, 22 bit address(ADDR10 to ADDR31))

 

 

 

EBI_BR0 - 0x2000_0803;

 

EBI_OR0 - 0xFFE0_0060;// 6 wait states

 

 

 

EBI_BR1 - 0x2020_0803;

 

EBI_OR1 - 0xFFA0_0060;

 

 

 

EBI_BR2 - 0x2060_0803;

 

EBI_OR2 - 0xFF60_0060;

 

 

 

EBI_BR3 - 0x20A0_0803;

 

EBI_OR3 - 0xFF5C_0060;

 

 

 

Output buffer enable(OBE) bit is enabled for all the EBI output signals, except Data lines in PCR registers.

 

 

 

After this configuration, I tried to access Address 0x20001000. But I could not read or write.

 

I probed the the CS0 signal and found that no chip select signal is generated by the EBI.

 

 

 

I am using 90 MHz system clock. I could not find any EBI module clock divider register in PXS3020 reference manual Rev.1.

 

I am not dividing the system clock since no register is given for EBI clock divider values(Not available in PXS3020 reference manual Rev.1).

 

 

 

 

 

Kindly help me to find the problem with the configuration.

 

 

 

 

 

Also I have the following queries.

 

1.) Are PXS3020 and MPC5675K register details same(Are PXS3020 and MPC5675K compatible?)?

 

2.) I created the project using CW eclipse IDE 10.4 and controller was selected as MPC5675K instead of PXS3020. Will it create any problem?

 

3.) How to configure EBI Clockout for slower speed(Please give the register address)?

 

4.) Are PCR register for EBI signal to be configured for week pull up?(I am not able to write in to the field)

 

5.) In section,EBI external calibration clock divider, it is given that devier value is 6 least significant  bits,

 

but  in register detail it is given as 6 most significant bits(Refered MPC5675K reference manuual Rev.10).

 

 

Thank you.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

1) These two devices are completely equal.

2) No, it cannot cause any problem.

3) Chapter 22.2.2.4.

“External calibration bus clock divider

EBI Clock is derived from sys_clk by means of a divider. The divider is in the Clock Generation Module at address 0xC3FE017F (byte) and uses the 6 least significant bits.

Divide ratio is n+1, which means a 0 in the register is div by 1, a 1 in the register is div by 2, and so on. The highest divide value is 0x3F which results in div by 64. Word (16 bit) and Long (32 bit) accesses are also possible but need to be aligned (0xC3FE017E for Word and 0xC3FE017C for Long).”

Apparently it is not defined in header file and surprisingly it is not defined as a register. You may access it like this:

(*(vuint32_t*)(0xC3FE017C)) = 0x01;

4) If you look at Table 48-11 you will see that default PCR value for EBI pads is 0bX0XX_0000_XX00_00XX. Note below this table says “For a bit value of X, the bit is not implemented for that PCRn register and its reset value is 0. Do not attempt to write to this reserved bit.” In other words these pads do not offer internal pull-ups/downs and these resistors must be connected externally.

5) I don’t know which register you are referring in this point, I have found only definition above (address 0xC3FE017F)

356 Views
mohammedshibin
Contributor I

First of all, Thank you David Tosenovjan. But I still need some clarification.

Now I am using EBI Clock as 30 MHz.

I am  using all the four chip selects and the details are given below.

1.) CS0 is connected to flash memory(2 MB) - No clock out, No burst memory access, 55 ns access time

2.) CS1 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time

3.) CS2 is connected to SRAM memory(4 MB) - No clock out, No burst memory access, 55 ns access time

4.) CS3 is connected to FPGA memory(256 KB)

The register configuration that I did is given below.

EBI_MCR - 0x0000_0005 (No external master, 16 bit data port, using 16 to 31 as data line, No multiplexed address and data lines, 22 bit address(ADDR10 to ADDR31))

EBI_BR0 - 0x2000_0803;

EBI_OR0 - 0xFFE0_0030; // 2 MB block size

EBI_BR1 - 0x2020_0803;

EBI_OR1 - 0xFFC0_0030;  // 4 MB block size

EBI_BR2 - 0x2060_0803;

EBI_OR2 - 0xFFC0_0030;  // 4 MB block size

EBI_BR3 - 0x20A0_0803;

EBI_OR3 - 0xFFFC_0030;  // 256 KB block size

After this, I tried access the extreme memory locations for each chip selects(lower address and upper address). But I found that chip selects are not asserting properly.

Would you please confirm the values for Option register(EBI_OR) for each chip selects.

Thank you.

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mohammedshibin
Contributor I

Hai,

I found it working after enabling the input buffer enable(IBE) bit for data lines in PCR register. Also I made the address mask value  same for each device( That is for my case, I gave 4MB address space for each device(EBI_OR1 - 0xFFC0_0030;  // 4 MB block size)).

But I have some issue with chip select signal when I use different address mask for each memory devices(since size of each device connected is different). That is chip select is not asserting when I try to access the upper memory for chip 2 and chip 3.

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