Hi, I am trying to determine the cause of an intermittent machine check exception from the EBI controller when performing a read. The EBI is used to communicated with an external SRAM device. I can single step through my code all day and never see a machine check exception when I do reads. If I run at full speed, I will get a machine check after reading the same address 15-100 times; it varies. The exception will also occur when reading any random address within the address space of my 256KB SRAM device. The exception occurs on an se_lhz instruction (specifically: se_lhz r31, 0 (r3), where r3 is 0x20540000). MCSR is 0x0008800C, indicating the exception occurs on a load instruction, but strangely the BUS_WRERR is also set. MCSRR1 is 0x00008000 which is different than the run-time value of MSR, 0x0200A000. I do have the bus monitor enabled and configured for ~1us timeout; the longest a transaction can take from the SRAM device is 800ns. So even if the exception is caused by a bus timeout, should I just get an EBI timeout flag and not an exception?
Here are the rest of my EBI settings:
MCR: 0x06000005
BMCR: 0x00000580
BR0: 0x200008a7
OR0: 0xE0000000
Thanks,
Sean
Looking back at my SVN log, I think I have this issue occurring consistently.
There is 96KB of ramtest SRAM at 0x40021A00, and this error only occurs after a march12 memory test on ramtest.
The error is reading from the EBI, which results in an IVOR1trap
MCSR is 0x0008800C
BUS_WRERR is also set
MCSSR0 is the last of the following:
e_lis r8,0x30000
e_add16i r3,r8,0x1408
se_lwz r3,0x0(r3)
se_lhz r31,0x4(r3)
MCSRR1 is 0x00008000
Here are the rest of my EBI settings:
MCR: 0x06000004
BMCR: 0x00001980
BR0: 0x20000827
OR0: 0xFFB00000
Why does this IVOR1trap only happen after the test on ramtest SRAM? I don't understand how reading and writing to SRAM is changing the behavior of the EBI bus read.
Could you specify used SRAM device?