I'm once given the advise that “You can choose part of the RAM memory, which will not be cached. So find the memory area, which is used by FEC and disable caching for this area” on the question “The FEC can't clear the R bit in the TxBD on MPC5675K ".
(Here is the weblink https://community.nxp.com/thread/394058)
I have studied the MMU and Cache chapter in the e200 core training relevant manual given by Martin carefully. And I have understood how they work and how to use them. But I still don’t know how to find the memory area which is used by FEC and how to disable caching for this area (there isn't the information in that document).
So can you give me some advise? I have been stuck in this for two weeks. I really have tried all my mays to solve this problem but still don't know how to conquer it.
Thank you very very much for your help.
The portion of SRAM where you have stored FEC buffer descriptors is needed to set for cache inhibited attribute i.e. to set up particular TLB entry in the MMU table. You may use following utility for simplifying of TLB configuration:
Note that every debugger or most of debuggers will be able to show MMU table in the screen like this:
Also I would like to point out following presentation, page 89-107: