Hi, specifically, in “PLL Off Mode” it must be full swing square wave clock input. In “Normal Mode” it is not so strictly defined, however square wave is expected output of external crystal oscillator.
In any case duty cycle of 50% is expected. EXTAL signal must fulfil voltage level defined by specifications VIHEXT, VILEXT
Sometimes minimum edge length is being required for input clock, however that's apparently not the case of this device, where I haven’t found such requirement.
