MPC5674F PLL Jitter on D_CLKOUT

[JDFAE]

A have a customer who is using an MPC5674F at 264MHz. They drive EXTAL with a 12MHz hybrid oscillator so the input source is stable.

On the D_CLKOUT pin, they are seeing more than a little jitter coming out of the PLL. They haven’t spent time trying to understand the ins and outs of jitter measurements to quantify exactly how much jitter there is.  There’s nothing visible for jitter on the 12MHz clock input, perhaps 1-2 percent on the D_CLKOUT pin.

They are concerned since the D_CLKOUT becomes the reference clock for a PLL in an external FPGA most likely exacerbating that PLL’s jitter.

They’re going back into layout soon and would like a recommendation of what can be done to minimize the 5674 PLL’s jitter. They have an LC filter on the VDDSYN input and are planning to get the components as close as possible to
the pin.

[lukaszadrapa · Accepted solution]

Hi,

max jitter is specified as +/-5% of CLKOUT frequency, so 1-2% is still within limit.

Yes, to keep the jitter as low as possible, it is necessary to use stable external clock, filter supply voltage enough (especially VDDSYN) and follow general PCB design rules...

Regards,

Lukas