MPC5674F EBI External Generated D_TA Timing Characteristics

[spetrofsky]

Configuration:      Using the MCP5674F power PC  EBI externaL 32 multiplexed bus mode and SETA=1

                                 for external D_TA;  the external peripheral supplies the /D_TA signal. to terminate the bus access

Question:             

1. Can D_TA externally generated transfer acknowledge go low for more than 1 clock period?
2. What happens if the D_TA were to go low for 3 clock periods?  
3. Would the cycle terminate on the D_TA going low or when it goes back High?

[davidtosenovjan]

Hi, I know the answer because I have already being dealt with the same question from different customer. However an answer does not provide too much clearness to this. The truth is we actually do not have specified situation when TA signal does not negate on time (i.e. TA pulse in longer than 1 clock).

Design has not considered the case where TA is asserted beyond the time shown in the diagrams in the reference manual. So, they cannot guarantee device behavior in this case. It seems to be extremely difficult to find out an answer and it would require a significant effort.

I just can recommend to negate TA signal in 1 clock period.