MPC5646C EMIOS IPF

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MPC5646C EMIOS IPF

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sandrine_labois
Contributor II

Hello,

I want to use the IPF function of the eMIOS to filter my entries.

I initialized my channel :

    EMIOS_0.CH[u8TorId].CCR.B.BSL = 0x0;          /* Use counter bus A (default) */
    EMIOS_0.CH[u8TorId].CCR.B.EDPOL = 1;        /* positive edge */
    EMIOS_0.CH[u8TorId].CCR.B.MODE = 0x00;    /* GPIO mode (input) */
    EMIOS_0.CH[u8TorId].CCR.B.UCPRE=0;         /* Set channel prescaler to divide by 1 */
    EMIOS_0.CH[u8TorId].CCR.B.UCPEN = 1;       /* Enable prescaler; uses default divide by 1 */
    EMIOS_0.CH[u8TorId].CCR.B.IF = 0x02;

Then to recover the level of my entry :

   val = EMIOS_0.CH[u8TorId].CSR.B.UCIN;

It is correct or not?

Thanks for your help.

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PetrS
NXP TechSupport
NXP TechSupport

Hi Sandrine,

The IPF ensures that only valid input pin transitions are received by the eMIOS Channel edge detector. The IPF is enabled by EMIOS_CHx.CCR[IF] field, configuring the filter latency.

In fact filter latency represents minimum pulse width which can pass the filter. Input signal is sampled on clock edge of selected clock(I guess rising edge); suppose minimum IF[0:3] = 0x0001 (meaning minimum pulse width of 2 filter clock periods), then if input signal is stable for 3 clock edges, the input signal propagates through filter.

FCK selects a clock for IPF; Prescaled clock means clock after channel prescaler, so you need to include both the global and channel prescaler into a calculation. Moreover the channel prescaler have to be enabled by UCPREN bit. The Main clock means the peripheral clock.

 

So if you have for example IF = 0b1000, FCK = 0, GPRE = 7, peripheral clock is 60Mhz then the minimum pulse width, which pass the filter should be

Width = (FLT_CLK periods+1) / [60Mhz/(GPRE+1)/(UCPRE+1)]

 

Thus for example for UCPREN=1 and UCPRE=0

Width = (16+1) / [60Mhz/(7+1)/ (0+1)] = 2.7us

BR, Petr

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