MPC5645S Dram driver

[deniszallot]

Good morning,

I work on the MPC5645S evaluation board.

I have written a DRAM driver.

I have noticed that the DCU can access this DRAM because when I modify the content of the DRAM, the TFT changes color.

On the other hand, I cannot have the E200z4 core write in it.

Also, the DRAM tests that I performed with the Green Hill debugger is OK

My ram is mapped at address 0x20000000. I hope that the DRAM at this address can be be accessed by the e200z4

Has anybody got a clue of what may be happening?

Thanks

[deniszallot]

Good afternoon,

I confirm that the CPU code cannot modify the DRAM even with the DCU not in operation.

There is no problem to modify the DRAM with the debugger. The ram tests that I perform with the debugger are OK.

I would be glad to have some source code that is ready to run on the  MPC5645S demo board that exercises the DRAM interface.

Best regards

[davidtosenovjan]

I have working code for DRAM configuration accessed by CPU. Please create new case with link to this MCU and will send it to you. Thanks for understanding:

https://community.nxp.com/docs/DOC-329745 

[davidtosenovjan]

If I understand you well you can modify DRAM content by debugger but not by CPU code as DRAM is occupied by DCU accesses, right?