MPC5644A DSPI: what duty cycle is supported?

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MPC5644A DSPI: what duty cycle is supported?

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EAlepins
Contributor V

Hi,

 

I am using the Qorivva MPC5644A's DSPI block. The Reference Manual describes the CTAR[DBR] and talks about various clock duty cycles. The Datasheet (Rev. 7) also talks about 33/66 duty cycle at §3.17.8 DSPI timing. However, when looking at the row #4 "SCK Duty Cycle" in the "Table 48. DSPI timing", the duty cycle seems pretty fixed to 50%:

 

Min = ½ tSC - 2

Max = ½ tSC + 2

 

1) Is there a typo here and tSC should be tSCK, i.e. a reference to row #1 of the table?

2) Why is non-50/50 duty cycles described in the RM and datasheet if this tables says only 50/50 duty cycle is supported?

 

Indeed, a 2ns variation on the faster clock (24.4ns) gives a maximum of 42/58 duty cycle...

 

Thanks.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Datasheet omits information that tSDC is only valid for 50:50 duty cycle configuration (based on DSPI_CTARn[DBR/CPHA/PBR] settings). For other SCK duty cycle configurations the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Datasheet omits information that tSDC is only valid for 50:50 duty cycle configuration (based on DSPI_CTARn[DBR/CPHA/PBR] settings). For other SCK duty cycle configurations the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

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EAlepins
Contributor V

Thanks. Can the documentation be corrected? (i.e. doc defect opened)

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Yes, sure. I'll report it.

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