The MPC5644A RM Rev 6 "Functional description" only talks about SMPL_PT field in the "220.127.116.11 Modified SPI/DSI transfer format (MTFE = 1, CPHA = 0)" chapter, No word about it in "18.104.22.168 Modified SPI/DSI transfer format (MTFE = 1, CPHA = 1)". However, according to its description in the MCR register, it is not tied to any particular CPHA setting.
It would be useful for us to delay by 1 or 2 system clocks the sample point of the DSPI SIN (we are in master mode, CPHA=1, CPOL=0). Can we interpreet the Data Setup Time for Inputs (tSUI) of the datasheet (Rev. 7) of 20 ns (for 5V input) as being the time between the SIN data being value and the sample point? If so, then the requirement would become 20 - 2*1/150MHz = 7 ns between data valid and clock rising edge.
Unfortunately the relationship between SMPL_PT and CPHA is not detailed in the MPC5644A RM. However I can confirm that the SMPL_PT bit is only valid in the case where MTFE = 1 and CPHA = 0. Here's an excerpt from another device's RM for the same SPI/DSPI module:
If you wish to use the SMPL_PT delays then you will have to change your CPHA to 0.
I hope this helps!