MPC5643L flash driver execution from SRAM

[ziomocci]

Hi all,

In our application, SSD C90FL drivers are executed directly from ROM.

Because I have encountered few read-while-write problems, I am moving drivers execution from ROM to SRAM.

Anyway, I am now in trouble with CACHE management (and CACHE enabled is needed by the high level SW control) during Flash driver execution from SRAM.

The only way would be to disable CACHE, but, as specified above, I would like to (or better, I have to) avoid CACHE disabling. 

So the question is: Is it posible (and if yes, how) to execute Flash drivers from SRAM and keep CACHE enabled at the same time?

Any suggestion would be very appreciated!!!

BR,

Andrea Mocci

[lukaszadrapa]

Hi Andrea,

there's no problem with SSD flash driver and cache. But there's a problem with cache and flash programming.

The best way is to keep the cache disabled during flash programming. If you need to keep the cache enabled then:

- configure the cache as write-through. Do not use write-back mode. (you have to ensure that you write directly to flash, not just to cache)

- invalidate the cache after each program/erase operation to ensure data coherency. You can invalidate whole cache or just required area.

- if you don't want to invalidate the cache each time, configure required flash area as cache inhibited using the MMU.

Regards,

Lukas

[ziomocci · Accepted solution]

Hi Lukas,

 Thank you for the fast answer.

CACHE invalidation seems a good solution and I am obtaining good results.

Thank you very much again.

BR,

Andrea Mocci