MPC5643L_PWMsignal change during one period

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MPC5643L_PWMsignal change during one period

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yanna
Contributor IV

I want to use MPC5643L to control a FB(full bridge) DC/DC converter ,which relies on EDMA,ADC.

Fllowing is circuit diagram and the PWM signal I want to get .

                           166553_166553.PNGcircuit diagram.PNG                          

                              166554_166554.PNGsteady waveform.PNG

 

The principle of the program is following(fig3), code is in attachment.

166555_166555.PNGprinciple of the program.PNG

 

Q1: I set shift_AD =200, shift_BC =400. During 10us, at first interrupt(T1CR),let shift=shift_BC; at second irst interrupt(T3CR),let shift=shift_AD;so we can get  the waveform should be ,and correspoding isr code is in attachment.

 

166556_166556.PNGQ1 drive.PNG

 

But the actual waveform looks like following(the PWM signal is changing during one period 5us):

166558_166558.PNGQ1_drive waveform.PNG

 

It’s unbeliveable. Becase no matter which case,the inner register (val register) should be constant during one period(5us),then ,how a constant val register produce a varing PWMA and PWMB driver signal during one period?

Does anyone has a clue?

 

Thanks very much!

Yanna

                       

 

Q2:during closeloop debuggingI power the MPC5643L only without input voltage,it means vc(control signal) should be very large,because there  no output voltage. So we can know that shift should be max value.

But the actual waveform is following.

  

In fact,the figure cannot descript the actual phenomenon,I saved a video(about actual PWM signal),but cant be put here.so I put it in this website,you can see it in this URL (PWM drive signal—在线播放—优酷网,视频高清在线观看  ) the first channel (yellow) is A.  the second channel is D .

 

Did anyone have the same experience, or have the idea which may cause this phenomenon?

 

 

Thanks very much!

Yanna

Original Attachment has been moved to: community_2016_10_25.rar

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petervlna
NXP TechSupport
NXP TechSupport

I have created PlexPWM configuration example according to DCDC needs.

Video demonstrate the measured PWM A0,B0, A2, B2 channels.

The example code is attached.

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yanna
Contributor IV

 Hi,peter

Thanks very much for your codes.

But I prefer to know which cause the constant val register produce the varying PWM signal,I dont think that the concept val2 must larger than val3 when corresponding sub is in complementary state is right.

I have got your code. I think some error may  exist in CTU or DMA, it's hard for me to find the reason which cause this phenomenon.

do you have any clue? or you still think the reason was the value of val2 and val3?

The video couldnt play properly ,it seems like a figure. But I can image the waveform through your codes.

Thanks very much!

Yanna

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

The constant is constant. It cannot change its values.

If you once program VALx registers their value change only on new write to this registers.

They do not change unintentionally.

I suggest you to perform debugging and find out if code or DMA is rewriting VALx registers.

Peter

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

Have in mind that in one period VAL2 compare must happen before VAL3.

As in the new period also new VALx values are loaded from double buffered registers.

The concept you have proposed would not work.

Peter

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yanna
Contributor IV

Hi,Peter

I dont think that you are right. Because I also try other method,but the result isnt the same.

EX1:

  I couldnt get result when I  wrote following code 

                                    DMA_CH1_ISR_num++;
                                    i=DMA_CH1_ISR_num%2;
                                   shift_AD=200;
                                  shift_BC=400;

                                 if(i==0) {shift=shift_AD;}
                                else if(i==1) {shift=shift_BC; }
                                 else{}

                               if (shift > shift_max ) { shift = shift_max; }
                               if (shift < shift_min) { shift = shift_min; }

                          //disable load of register buffer to unlock VALx registers
                             FLEXPWM_0.MCTRL.B.CLOK = 1;
                            FLEXPWM_0.SUB[1].VAL[2].R = 600-shift-FLEXPWM0_DEADTIME;// sub1 val2 value
                            FLEXPWM_0.SUB[1].VAL[3].R = 1200-shift-FLEXPWM0_DEADTIME;

                           //enable load of register buffer
                          FLEXPWM_0.MCTRL.B.LDOK = (FLEXPWM_0.MCTRL.B.LDOK | 0x1); 
                           EDMA.DMAINTL.R = 0x02;

EX2:

I could get the result I want when I wrote the following  code:

                                     DMA_CH1_ISR_num++;
                                    i=DMA_CH1_ISR_num%2;
                                   shift_AD=200;
                                  shift_BC=400;

                                 if(i==0)

                                {

                                         shift=shift_AD;

                                         

                             FLEXPWM_0.MCTRL.B.CLOK = 1;
                              FLEXPWM_0.SUB[1].VAL[3].R = 600-shift-FLEXPWM0_DEADTIME;// sub1 val2 value
                  //           FLEXPWM_0.SUB[1].VAL[2].R = 1200-shift-FLEXPWM0_DEADTIME;

                            FLEXPWM_0.MCTRL.B.LDOK = (FLEXPWM_0.MCTRL.B.LDOK | 0x1);

                                                  

                                 }
                                else if(i==1)

                            {

                                  shift=shift_BC;

                                  

                             FLEXPWM_0.MCTRL.B.CLOK = 1;
                      //       FLEXPWM_0.SUB[1].VAL[3].R = 600-shift-FLEXPWM0_DEADTIME;// sub1 val2 value
                            FLEXPWM_0.SUB[1].VAL[2].R = 1200-shift-FLEXPWM0_DEADTIME;       

                            FLEXPWM_0.MCTRL.B.LDOK = (FLEXPWM_0.MCTRL.B.LDOK | 0x1);

                            }
                                 else{}

                         //      if (shift > shift_max ) { shift = shift_max; }
                        //       if (shift < shift_min) { shift = shift_min; }

                        I couldnt get the result of the EX2    if you are right . Beause Val2 always larger than    Val3.   

                        oh,I forget to tell the other detail, A and B is a complementary pair, and C and D is the other complentary pair.         

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yanna
Contributor IV

Hi,Peter

was the consept wrong when sub[0]  control the sub[1]?

I cannot find corresponding text that  VAL2 compare must happen before VAL3  in RM.

Where could I find it ? or it wasn't in RM ,only someone know from experience.

Thanks very much!

Yanna.

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