I finally had a time to look at your excel.
CF - Inject multibit ECC error into Flash memory by SW.
CF - IS triggered when self test configuration is loaded from shadow flash and an error is detected in SSCM STCU device configuration client. - This fault is possible to trigger by SW however the shadow flash STCU content is defined in reference manual. Not following manual and writing incorrect data into for STCU into shadow flash can emulate this fault state and trigger this fault. I will be very careful here and not try to write incorrect data into shadow flash.
CF[23 -24] - HW fault which you cannot emulate by SW.
CF - Unintended activation of STCU in application mode. Not possible to trigger by SW.
CF[28-31] - Unintended activation of TCU signals other then in NXP factory tests. Not possible to emulate by SW.
CF - Error signals in JTAG. Possible to emulate by disconnecting JTAG from device in debug mode under power. Disconnect JTAG few times from running application and you will get this fault.
NCF - Core watchdog_0 expiration - configure and let expire core watchdog_0
NCF - Core watchdog_1 expiration - configure and let expire core watchdog_1
NCF[2 - 3] - Unlock PLL0 - for example disconnect XTAL which supply acitve PLL
NCF - Mode transition to reset mode.
NCF[22-24] - When ballast transistor is bypassed (accidental malfunction / failure). Not possible to trigger by SW.
We only have description of faults in reference manual.
But I assume most of the faults can be understand from this description.
First of all you have to determine which faults have influence on your system and makes sense to test reaction path on them.
Basically I want to understand when exactly all these NCF errors will originate & its source description, so that I can analyze whether I have consider particular NCF in my design or not.
Is there any way you can help me to understand.
Thanks for your earlier informations.
I have created AN5259. Actually at this moment there is no other FCCU fault description then Reference manual.
I have in plan to create such documents for other MPC5xxx processors, however I have no time schedule atm.
The reason is that noone asked NXP to do such application notes.
In case of any questions do not hesitate to ask me.