MPC5643L BIST operation for LVD/HVD

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MPC5643L BIST operation for LVD/HVD

292 Views
rakeshshetty
Contributor II

Hello,

I need some information's regarding 1.2V core voltage LVD/HVD operation in MPC5643L Microcontroller.

From the datasheet I understood that the 1V2 core voltage will be monitored for both LVD, and HVD during BIST operation which comes under PHASE3 of the Reset sequence. The voltage detectors themselves have a hardware based self-checking feature.In case the main voltage detector detects over or under voltage during normal operation of the Microcontroller  a ‘ destructive reset ‘ is triggered.

Now, I want to know what are all the software actions are required (If any) to execute this operation like some test case. How do we know that is is successfully done.

Any additional information on this topic is useful.

Thanks in Advance.

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3 Replies

108 Views
petervlna
NXP Employee
NXP Employee

Hi,

Actually the voltage regulator tests are fully handled in hardware.

The voltage regulators monitor the LVD and HVD all the time after Power is applied. So if during your application run they spot drop or peak reset is immediately generated to prevent any issues by micro itself.

After reset user should read the RGM (reset generation module) to find out the reset reason.

Registers FES and DES will give you the information. Those registers should be handled by application.

Additionally micro after such reset is going into the SAFE mode to prevent any damage to external devices like motor, etc..

Peter

108 Views
rakeshshetty
Contributor II

Hi Peter,

Thank you for this information.

I got this doubt when I was reading safety Manuel, it is mentioned that "Core voltage LVD and HVD implement a hardware assisted self-test that needs to be initiated by software once after the boot. and also "The software actions are required to check the run of the BIST procedure, generating non-critical faults (NCFs) or critical faults (CF) conditions for the FCCU module".

Could you please give more information on above points?

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108 Views
petervlna
NXP Employee
NXP Employee

Ok so,

The micro implements Voltage detector BISTs. In order to verify the correct functionality of detectors.

1. This voltage BIST is automatically executed during reset phase after power on reset is applied.

2. As higher safety classes also require to execute voltage BIST during application execution there is additional possibility to start BIST via SW. For this purpose there is PMUCTRL control register (PMUCTRL_CTRL). During this self test reset reactions are masked.

The results are stored in the PMUCTRL_FAULT register.

When bits in this register are set the corresponding FCCU flags are set.

Before clearing the HVD and LVD critical fault by means of the FCCU, you must clear the following four
pending fields in the PMUCTRL_IRQS register:
• MLVDP
• BLVDP
• MHVDP
• BHVDP

Peter