MPC560xB - Bad RAM initialization at startup

[romainbenet]

Hi,

in a previous post I ask why in the following startup code

"

   /* SRAM initialization code*/
   lis r11,L2SRAM_LOCATION@h
   ori r11,r11,L2SRAM_LOCATION@l

   /* Loops to cover L2SRAM, stmw allows 128 bytes (32 GPRS x 4 bytes) writes */
   lis r12,L2SRAM_CNT@h
   ori r12,r12,L2SRAM_CNT@l
   mtctr r12

   init_l2sram_loop:
   stmw r0, 0(r11) /* Write 32 GPRs to SRAM*/
   addi r11,r11,128 /* Inc the ram ptr; 32 GPRs * 4 bytes = 128B */
   bdnz init_l2sram_loop /* Loop for 48k of SRAM */

"

SRAM data is not initialized to value 0x00 in all bytes and you answer me that 

" There in no need to have ram initialized with 0x0000 0000 patern.

  And it is also not recommended to have all 0 in SRAM.

  Your RAM will be initialed with R0 to R31 GPRs in 128bytes loops. And the address on R11 will be incremented by 128B. "

What is the reason to avoid SRAM initialization to pattern 0x0000 0000 ?

Best regards,

Romain

[davidtosenovjan]

The whole SRAM needs to be written by any value. Important is that it must be 64-bit write, to completely define ECC
code for data unit.
Users sometimes use special patterns having meaning of certain opcodes as 'nop' or branch to itself, but it is not necessary, it can be cleared.

Pay attention to section 1.1 of AN5200:

AN5200 - Error Correcting Codes Implemented on MPC55xx and MPC56xx 

[romainbenet]

Hi,

When I read your application note section 1.1 it says that " the whole SRAM is deleted or written by any value, however it must be either 64-bit write or 32-bit write" and when I read the table 2 which indicates which component is associated to 32 or 64 bits write my target (MPC5604B) as other MPC560xB uses the ECC 32+7.

So is it possible that I can initialize the SRAM by 32bits access with pattern 0x0000 0000 ?

Best regards,

Romain

[davidtosenovjan]

Yes, you can. Actually it can be either 32-bit or 64-bit write with this device.

[romainbenet]

Thank you for your help.

Romain