MPC5606s clock configuration

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MPC5606s clock configuration

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mhogun
Contributor I

HI,

 

I am using one sample code for clock generation in mpc5606s controller.

the below line says is PLL0 is 64MHz ,but i am got confusion .kindly explain me how it is  64 MHz?

 

CGM.FMPLL[0].CR.R = 0x02400100;    /* 8 MHz xtal: Set PLL0 to 64 MHz */

 

Also kindly give a idea about clock generation in mpc5606s controller.it will be more helpful.

 

Thank you  in advance.

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martin_kovar
NXP Employee
NXP Employee

Hello,

CGM.FMPLL[0].CR.R = 0x02400100 sets the following bits in CR register:

IDF = 0

ODF = 2

NDIV = 64

According the tables 8-22, 8-23 and 8-24 in reference manual:

Input divide ratio is 1 (IDF = 0)

Output divide ratio is 8 (ODF = 2)

Loo divide ratio is 64 (NDIV = 64)

Fsys = (input_clock * NDIV) / (IDF * ODF)

Fsys = (8MHz * 64) / (1 * 8)

Fsys = 64MHz

For more information, please read chapter Clock Description in MPC5606 Reference manual.

http://www.nxp.com/assets/documents/data/en/reference-manuals/MPC5606SRM.pdf 

Regards,

Martin

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