MPC5604P - Codewarrior default initialization

[steffenrose]

Hello,

do anybody know the sense of this initialization in the default created file MPC5604P_M26V_HWInit.c

__asm void INIT_Derivative(void)

{

nofralloc

    /* MPC5604P_M26V SRAM initialization code                                 */

    lis r11,L2SRAM_LOCATION@h       /* Base of SRAM, 64-bit word aligned */

    ori r11,r11,L2SRAM_LOCATION@l

    li r12,320        /* Loops to cover 40K SRAM; 40k/4 bytes/32 GPRs = 320 */

    mtctr r12

    init_l2sram_loop:

        stmw r0,0(r11)        /* Write 32 GPRs to SRAM                     */

        addi r11,r11,128      /* Inc the ram ptr; 32 GPRs * 4 bytes = 128B */

        bdnz init_l2sram_loop /* Loop for 40k of SRAM                      */

    blr

}

I understand and see, that the registers are not 0. There are different values. Especially r11 is changed in every loop.

Why the init code write the "random" register values to the complete RAM?

bye

Steffen

[lukaszadrapa]

Hi Steffen,

The internal SRAM features Error Correcting Code (ECC). Because these ECC bits can contain random data after the device is powered on, all SRAM locations must be initialized before being read by application code. This is done by executing 64-bit writes or 32-bit writes (depends on device) to the entire SRAM block. The value written does not matter at this point, so the Store Multiple Word instruction will be used to write 32 general-purpose registers at a time.

From reference manual:

16.5 SRAM ECC mechanism

The SRAM ECC detects the following conditions and produces the following results:

• Detects and corrects all 1-bit errors

• Detects and flags all 2-bit errors as non-correctable errors

• Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all ones, asserts an

error indicator on the bus cycle, and sets the error flag

SRAM does not detect all errors greater than 2 bits.

Internal SRAM write operations are performed on the following byte boundaries:

• 1 byte (0:7 bits)

• 2 bytes (0:15 bits)

• 4 bytes or 1 word (0:31 bits)

If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated

across the 32-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.

If the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the following occurs:

1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or

flagging errors.

2. The write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the data bus.

3. The ECC is then calculated on the resulting 32 bits formed in the previous step.

4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then

written to SRAM.

[steffenrose]

Hello Lukas,

In this case it is only required after a Power on Reset, right?

I want to "save" data during Software Reset cycles.

Thank you very much.

bye

Steffen

[steffenrose]

Re: Uninitialized variable initialized to zero at power up?

[lukaszadrapa · Accepted solution]

I found example in my repository that shows how to keep variable uninitialized during resets. See please attached project. There's variable reset_counter that counts the resets caused by SWT.

And here is the description which I wrote for this example:

1. Copy __start.c file from CodeWarrior installation folder to your project. Add this file to project.

2. Modify function __init_data() in __start.c as shown in example.

3. Open linker file and modify GROUP for internal_ram in this way (add myUData):

GROUP : {

  .__uninitialized_intc_handlertable ALIGN(2048) : {}

  .data : {}

  .myIData: {}

  .sdata : {}

  .sbss : {}

  .sdata2 : {}

  .sbss2 : {}

  .bss : {}

  _myDataStart=.;

  .myUData: {}

  _myDataEnd=.;

  } > internal_ram

4. Open file MPC5604P_M26V_HWInit.c and search for INIT_Derivative() function. This function initializes whole RAM due to ECC. It is necessary to re-write this code – we will skip initialization in case of watchdog reset. See example code.

5. And finally see the main.c.

Notice that only software reset will ensure that SRAM is not corrupted by reset. All other resets are asynchronous, so it may happen that data will be corrupted if write operation is terminated by reset (it depends when the reset occurs). In this case, ECC error can occur in SRAM. So, you can initialize SRAM only after power-on but I strongly recommend to carefully handle exceptions and possible ECC errors. One option would be to read whole SRAM after reset to ensure that there are no ECC errors (i.e. no exception will occur during reading). See this document for more details:

Error Correcting Codes

Regards,

Lukas

[steffenrose]

Hi,

a Software Reset is the only required Reset to hold the data. Thank you very much.