MPC5604E I2C Issues

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MPC5604E I2C Issues

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supreethkoushik
Contributor I

Hi All,

I'm trying to configure ADV7182 Digitizer connected to MPC5604E uC using I2C but I am facing some issues, namely

1.   IBDR register is not getting written [It is the register which initiates data Transmit or receive]

2.   I2C initialization sequence in reference manual of MPC5604E [Pg no. 857] mentions about the IBDIS bit of IBCR       register, but IBDIS doesn't exists.

3.   It looks like Frequency Divider Register IBFD sets the data rate, It's confusing, mentioned as SCL divider.

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) there should be no issue with writing the IBDR unless the module clock is gated within ModeEntry module, check respective ME_PCTL register setting.

2) this is a typo, it should be “Clear the IBCR[MDIS] field…”

3) see for example this post, https://community.nxp.com/message/657252#comment-657391. Only calculate with your module clock.

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) there should be no issue with writing the IBDR unless the module clock is gated within ModeEntry module, check respective ME_PCTL register setting.

2) this is a typo, it should be “Clear the IBCR[MDIS] field…”

3) see for example this post, https://community.nxp.com/message/657252#comment-657391. Only calculate with your module clock.

BR, Petr

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supreethkoushik
Contributor I

Hey Petr,

Thank You for the quick reply,

We are using System CLK at 60MHz, I have attached the image from reference manual One is the clock architecture and another one where Module Clock is connected to Sys_Clk and BIU to IPS@Sys_Clk.

In MPC5604E, from where does the I2C module is clocked from?

pastedImage_3.png

pastedImage_2.jpg

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PetrS
NXP TechSupport
NXP TechSupport

calculate bit rate based on Sys_Clk

BR, Petr

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supreethkoushik
Contributor I

Hi Petr Stanci

Thanks for the response. It was very helpful. We were able to bring up the I2C on our prototype board.

Regards,

Supreeth

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