Hi,
I have been trying to test offline BIST for quite some time and haven't been successful. I followed AN5288 and tried the script provided, and still was not successful.
Here is the screenshot of the registers after reset:
As you can see, it was set up to run both MBIST & LBIST. The pointer in CFG points to MBIST0. MY XOSC is @ 32MHz, so I set PLL_CFG to 8, 2, 25 (0x19) to set the clock to 50 MHz. (32 x 25 / 16). My watchdog is set to 61.44ms, like what the application note was showing.
Once out of reset, the ERR_STAT register shows there were some recoverable faults, and the watchdog timer has expired. My MBSL / MBSM / MBSH / MBEL / MBEM / MBEH are all 0's which I think means none of them has run. I see contents in MISREHn / MISRELn / MISRRLn / MISRRHn so I think the registers are being written. I am just not sure why it's not being executed.
This is my MBIST control registers settings.
I also have a non-OTP part, which means I can keep erasing & rewriting UTEST region (0x400300 ~) region. I am not sure if that matters but I am erasing & rewriting the entire DCF records. I've attached the DCF record I am using to test it.
Is anything I am doing look incorrect, or suspicious? Any help will be appreciated.
Thanks,
Ben
Hi Peter,
Thanks for the reply. You may have forgotten to include screenshot. I don't see your ERR_STAT.
I tried to increase the WDG value to 3,000,000 (0x2DC6C0). I am still experiencing similar register values. I don't see any updates on the LBIST / MBIST status registers, so I don't think any of them ran. One thing I notice is that it takes ~5.5 seconds for the WDG to expire and get out of reset, whereas it should've been 3.8 seconds, according to the contents in AN5288 (it says @50 MHz, 0xBB80 = 61.44 ms so 0x2DC6C0 = 3.84 ms). It's interesting that if I do the same calculation with the clock frequency of 32 MHz, which is my XOSC, it would take 6 seconds for the WDG to expire. I am curious if the PLL is not being locked, and causing STCU2 to not run at all.
Does it make sense? If so, how would I ensure that I am setting STCU_PLL_CFG values correctly? I got these values (RFDPHI = 9, PREDIV = 2, MFD = 25) using the worksheet I got from NXP, ensuring that VCO is between 600 ~ 1250V.
Here is the screenshot of the values with WDG set to 0x2DC6C0.
Any comments will be appreciated.
Thanks,
Ben
