Instruction Set Document for MPC56xx processor

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Instruction Set Document for MPC56xx processor

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vijaysrinivasa
Contributor II

Hello

 

I need a instruction set for MPC56xx micro controller. Please give if anyone having.

 

Best Regards

vijay

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ludwigschreier
Contributor IV

Hello,

maybe this is also relevant: The VLE Programming Interface Manual (VLE PIM) is a reference guide for high-level programmers.

But my question is, are there any instruction set documents for MPC57xx?

Kind regards

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martin_kovar
NXP Employee
NXP Employee

Hello Ludwig,

MPC57xx cores support VLE instruction set only, so you can use the document I posted above or the the document you posted here.

There is only one exception, MPC5777C supports VLE and also BookE instruction set.

Regards,

Martin

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vijaysrinivasa
Contributor II

Hello Martin

I am not able to figure it out which instruction to use from  MPCxxxx instruction set for PC and PSW. what are the  actual Program counter(PC) and program status word(PSW) equivalent  registers in MPCxxxx instruction set.

I have a renesas v850 assembly code below,  now i have use same using MPC5606B instruction set

first part:-

stsr 0, r1   /* Store the contents of eipc values in register 1 */ 
stsr 1, r5  /* Store the contents of eipsw in register 5 */              

                 /*EIPC and EIPSW : -Interrupt status saving registers , EIPC and EIPSW are used to save the status when an                  interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter                          (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW*/

second part :

ori 0x20, r5, r5 /* Disabling the interrupts*/

ori 0x40, r5, r5 /*Exception is being processed.:-Indicates that an exception is being processed. This bit is set to 1 when                             an exception occurs. Even if this bit is set, interrupt requests are acknowledged*/

In  second part i can use MSR register bit EE to disable the interrupt (if not correct please let me know which one to use and how to use it), 

In second part , in MPXxxx instruction set Which register says the exception handling , which register i have to access to say that i have handled the exception occurrence.

best Regards

vijay

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ludwigschreier
Contributor IV

Hi Vijay, did you check EREFRM_2-0.pdf Chapter 7? KR

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martin_kovar
NXP Employee
NXP Employee

Hello,

please see attachment in this post.

Regards,

Martin

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vijaysrinivasa
Contributor II

Hello Martin 

Thank you for the help. You are doing a great job

Do you have any example for an return from interrupt subroutine (through PUSH and POP strategy has done , may be different instructions for power PC ) in assembly language.

Best regards

vijay

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martin_kovar
NXP Employee
NXP Employee

Hello Vijay,

there is no PUSH, POP strategy with MPC5 microcontrollers. Please see following code. It is simple prolog and epilog used for MPC56xx microcontrollers.

IVOR4_Handler:
prologue:
    e_stwu      r1,-0x50 (r1)           ;# Create stack frame and store back chain
    e_stmvsrrw      0x0c (r1)           ;# Save SRR[0-1] (must be done before enabling MSR[EE])
    se_stw      r3, 0x08 (r1)           ;# Save working register (r3)
    e_lis       r3, INTC_IACKR@ha       ;# Save address  of INTC_IACKR in r3
    e_lwz       r3, INTC_IACKR@l(r3)    ;# Save contents of INTC_IACKR in r3 (this is vector table address)
    wrteei      1                       ;# Set MSR[EE] (must wait a couple clocks after reading IACKR)
    se_lwz      r3, 0x0(r3)             ;# Read ISR address from Interrupt Vector Table using pointer
    e_stmvsprw      0x14 (r1)           ;# Save CR, LR, CTR, XER
    se_mtLR     r3                      ;# Copy ISR address (from IACKR) to LR for next branch
    e_stmvgprw      0x24 (r1)           ;# Save GPRs, r[0,3-12]
    se_blrl                             ;# Branch to ISR, with return to next instruction (epilogue)

epilogue:
    e_lmvsprw       0x14 (r1)           ;# Restore CR, LR, CTR, XER
    e_lmvgprw       0x24 (r1)           ;# Restore GPRs, r[0,3-12]
    e_lis       r3, INTC_EOIR@ha        ;# Load upper half of INTC_EOIR address to r3
    mbar                                ;# Ensure prior clearing of interrupt flag conmpleted.
    wrteei      0                       ;# Disable interrupts
    e_stw       r3, INTC_EOIR@l(r3)     ;# Load lower half of INTC_EOIR address to r3 and
                                        ;# write contents of r3 to INTC_EOIR
    se_lwz      r3, 0x08 (r1)           ;# Restore working register (r3) (original value)
    e_lmvsrrw       0x0c (r1)           ;# Restore SRR[0-1]
    e_add16i    r1, r1, 0x50            ;# Reclaim stack space
    se_rfi                              ;# End of Interrupt Handler - re-enables interrupts

I am also attaching you EABI document, which could be useful if you work with MPC microcontrollers.

Regards,

Martin

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vijaysrinivasa
Contributor II

Hello Martin 

Thank you.This is valid information.

In above example what i understood is , when interrupt happens this IVOR4_Handler will execute. with what extension i have to save this file? like .c or .asm or? and place in my project and compile the project.

Please share Application note for above example , for my better understanding.

Best regards

vijay

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martin_kovar
NXP Employee
NXP Employee

Hello Vijay,

please look at the AN2865. There is pretty good description, how interrupts work. But I think better way is to open some example, go through the files and explore how it works. And if you have microcontroller the best way is to download some example to microcontroller and debug it step by step.

Here is link for AN2865:

http://www.nxp.com/assets/documents/data/en/application-notes/AN2865.pdf?fsrch=1&sr=1&pageNum=1 

and here is link for example list available here at community:

https://community.nxp.com/docs/DOC-329623 

Hope it helps.

Regards,

Martin

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