Hello,
I am trying to implement SIPI for the communication between two MPC5777Cs.
Is there a software example for SIPI/LFAST on the MPC5777C available?
I have the example software of AN5134 but have problems adapting the LFAST setup (GPIOs + initialisation) to the MPC5777C as the slave is unable to receive ICLC messages from the master.
Details:
Previously I had implemented Zipwire for a pair of MPC5777M EVBs using the software example of AN5134. I re-used the LFAST initialisation procedure for the MPC5777C, changing only the pin definitions and the PLL frequency divider (due to the lower data rate as described by errata ERR007511).
The pins are defined as following:
- Both:
SIU.PCR[212].R = 0x1100; //RX_P PIN: PA = 0xb100 (Alternate 3), IBE = 1
SIU.PCR[213].R = 0x1100; //RX_N PIN: PA = 0xb100 (Alternate 3), IBE = 1
SIU.PCR[208].R = 0x12C0; //TX_P PIN: PA = 0xb100 (Alternate 3), OBE = 1, DSC = 0b11 (maximum driver strength)
SIU.PCR[209].R = 0x12C0; //TX_N PIN: PA = 0xb100 (Alternate 3), OBE = 1, DSC = 0b11 (maximum driver strength)
- LFAST-master:
SIU.PCR[210].R = 0x1100; //SIPI_REFCLK input
- LFAST-slave:
SIU.PCR[210].R = 0x1200; //SIPI_REFCLK pin is enabled. Enable output buffer and assign pad to SIPI_REFCLK function (20 MHz).
The problem is that the LFAST-slave does not receive the ICLC-Command to enable the Tx interface. The data is sent by the LFAST-master however as seen using an oscilloscope (only the TX_P signal of the master is shown):
The LFAST synchronisation pattern and the ICLC-Payload (0x31) can be recognized. The slave shows no reaction to the packet however and the corresponding interrupt pending bit (RIISR_ICTEF) is not asserted.
Regards,
Bernd
