#if defined(BRSASR_ENABLE_OS_MULTICORESUPPORT)
___asm(;/* skip RAM init for slave cores */)
__as1(mfspr r3, PIR ;/* read out CPU ID PIR */)
__as1(se_cmpi r3, BRS_CPU_STARTUP_ID ;/* if current CPU is NOT startup core? */)
___asm(se_beq _startupF ;/* proceed with section F */) //cjh
#endif
___asm(;/*****************************************************************************/)
___asm(;/* (F) INIT Core0 RAM */)
___asm(;/*****************************************************************************/)
#if defined(BRSASR_ENABLE_OS_MULTICORESUPPORT)
___asm(_InitCore0Ram:)
#endif
___asm(;/*****************************************************************************/)
___asm(;/* (D) Initialise Core 0 Local Data SRAM ECC */)
___asm(;/*****************************************************************************/)
__as1(e_lis r5, __CORE0_LOCAL_DMEM_SIZE@h; /* highbytes - r11 holds start address of the RAM */)
#if defined (BRSHW_INSTRUCTION_SET_VLE)
__as1(e_or2i r5, __CORE0_LOCAL_DMEM_SIZE@l; /* lowbytes - r11 holds start address of the RAM */)
#else
__as2(e_ori r5,r5, __CORE0_LOCAL_DMEM_SIZE@l; /* lowbytes - r11 holds start address of the RAM */)
#endif
__as2(e_srwi r5,r5, 0x7; /* # Divide SRAM size by 128 */ )
___asm(se_mtctr r5; /* # Move to counter for use with "bdnz" */ )
__as1(e_lis r5, __CORE0_LOCAL_DMEM_BASE_ADDR@h; /* highbytes - r11 holds start address of the RAM */)
#if defined (BRSHW_INSTRUCTION_SET_VLE)
__as1(e_or2i r5, __CORE0_LOCAL_DMEM_BASE_ADDR@l; /* lowbytes - r11 holds start address of the RAM */)
#else
__as2(e_ori r5,r5, __CORE0_LOCAL_DMEM_BASE_ADDR@l; /* lowbytes - r11 holds start address of the RAM */)
#endif
___asm(core0_ldmem_loop:)
__as1(e_stmw r0,0(r5); /* # Write all 32 registers to SRAM */)
__as2(e_addi r5,r5,128; /* # Increment the RAM pointer to next 128bytes */)
___asm(e_bdnz core0_ldmem_loop; /* # Loop for all of SRAM */)
___asm(;/*****************************************************************************/)
___asm(;/* (D) Initialise Core 0 Local Instruction SRAM ECC */)
___asm(;/*****************************************************************************/)
__as1(e_lis r5, __CORE0_LOCAL_IMEM_SIZE@h; /* highbytes - r11 holds start address of the RAM */)
#if defined (BRSHW_INSTRUCTION_SET_VLE)
__as1(e_or2i r5, __CORE0_LOCAL_IMEM_SIZE@l; /* lowbytes - r11 holds start address of the RAM */)
#else
__as2(e_ori r5,r5, __CORE0_LOCAL_IMEM_SIZE@l; /* lowbytes - r11 holds start address of the RAM */)
#endif
__as2(e_srwi r5,r5, 0x7; /* # Divide SRAM size by 128 */ )
___asm(se_mtctr r5; /* # Move to counter for use with "bdnz" */ )
__as1(e_lis r5, __CORE0_LOCAL_IMEM_BASE_ADDR@h; /* highbytes - r11 holds start address of the RAM */)
#if defined (BRSHW_INSTRUCTION_SET_VLE)
__as1(e_or2i r5, __CORE0_LOCAL_IMEM_BASE_ADDR@l; /* lowbytes - r11 holds start address of the RAM */)
#else
__as2(e_ori r5,r5, __CORE0_LOCAL_IMEM_BASE_ADDR@l; /* lowbytes - r11 holds start address of the RAM */)
#endif
___asm(core0_limem_loop:)
__as1(e_stmw r0,0(r5); /* # Write all 32 registers to SRAM */)
__as2(e_addi r5,r5,128; /* # Increment the RAM pointer to next 128bytes */)
___asm(e_bdnz core0_limem_loop; /* # Loop for all of SRAM */)
___asm(;/*****************************************************************************/)
___asm(;/* (F) INIT INTERRUPT VECTOR BASE REGISTER */)
___asm(;/*****************************************************************************/)
#if defined(BRSASR_ENABLE_OS_MULTICORESUPPORT)
___asm(_startupF:)
#endif
#define D_CACHE_ENABLE
___asm(;/*****************************************************************************/)
___asm(;/* D_Cache enable */)
___asm(;/*****************************************************************************/)
#ifdef D_CACHE_ENABLE
___asm(DCACHE_CFG:;)
__as1(e_li r5, 0x2:smileywink:
__as1(mtspr l1csr0,r5;)
__as1(e_li r7, 0x4:smileywink:
__as1(e_li r8, 0x2:smileywink:
__as1(e_lis r11, 0xFFFF:smileywink:
__as1(e_or2i r11, 0xFFFB:smileywink:
___asm(DCACHE_INV:;)
__as1(mfspr r9, l1csr0;)
__as2(and. r10, r7, r9;)
___asm(e_beq DCACHE_NO_ABORT;)
__as2(and. r10, r11, r9;)
__as1(mtspr l1csr0, r10;)
___asm(e_b DCACHE_CFG;)
___asm(DCACHE_NO_ABORT:;)
__as2(and. r10, r8, r9;)
___asm(e_bne DCACHE_INV;)
__as1(mfspr r5, l1csr0;)
__as2(e_ori r5, r5, 0x0001:smileywink:
___asm(se_isync;)
___asm(msync;)
__as1(mtspr l1csr0, r5;)
#endif
__as1(e_li r0, 0 ;/* Clear r0 */)
#if !defined (BRS_DERIVATIVE_PC582101)
__as1(e_lis r0,_VECTORTABLE_START_ADDR@h ;/* r11 holds base address of the L2SRAM 64-bit word aligned*/)
# if defined (BRSHW_INSTRUCTION_SET_VLE)
__as1(e_or2i r0,_VECTORTABLE_START_ADDR@l
# else
__as2(e_ori r0,r0,_VECTORTABLE_START_ADDR@l;)
# endif
#endif
__as1(mtspr 63, r0 ;/* set IVPR */)
.......
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