Identify the source of the interrupt(NMI)?

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Identify the source of the interrupt(NMI)?

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vaibhav_sharma
Contributor III

Microcontroller: MPC5777C

Interrupt sources-

1. [EXTERNAL] SBC is triggering interrupt on the NMI line of controller handled by IVOR1.

2. [INTERNAL] FCCU NMI test raises a NMI request handled by IVOR1 too.

Both are being routed to core0. The status bit is the same, i.e., SIU_EISR.B.NMI0 & NMI bit in the MCSR register, for both the cases. So, is there any other status bit by which I can identify the exact cause of that NMI interrupt.

Same is the case for machine check exception handled by IVOR1-> 

1. SRAM single bit error generates it.

2. Illegal memory access by any of the bus master can generate it.

For this, the single status bit MCP is available in the MCSR register. 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

a) The only way how to distinguish is to examine all sources you have configured to possibly generate NMI (i.e. in this case FCCU registers), and if it is not FCCU fault, then you may suppose it is external NMI line.
Better option is to configure external NMI line to invoke IVOR0 (pay attention to SIU_DIRER register).

b) Single bit ECC error does not cause machine check. It must be multi-bit ECC error. For that there several flags in MCSR register (IF/LD/ST/BUS_IRERR/DRERR/WRERR)

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davidtosenovjan
NXP TechSupport
NXP TechSupport

a) The only way how to distinguish is to examine all sources you have configured to possibly generate NMI (i.e. in this case FCCU registers), and if it is not FCCU fault, then you may suppose it is external NMI line.
Better option is to configure external NMI line to invoke IVOR0 (pay attention to SIU_DIRER register).

b) Single bit ECC error does not cause machine check. It must be multi-bit ECC error. For that there several flags in MCSR register (IF/LD/ST/BUS_IRERR/DRERR/WRERR)

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