How to set the input clock for Master LFST of s32r274

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How to set the input clock for Master LFST of s32r274

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liub
Contributor I

Clock source setting:

//Auxiliary Clock 8
// LFAST DIVIDER COMES FROM AUX CLOCK SELECTOR 8
#if(CONFIGURED_AS_MASTER)
CGM.AC8_SC.B.SELCTL=5; /*! Input from LFAST-SysClk Pin */
CGM.AC8_DC0.R=0x80000000;
#else
CGM.AC8_SC.B.SELCTL=2; /*! PLL0 PHI for Aux Clock 0 */
CGM.AC8_DC0.R=0x80090000; /*! Aux Clock 1 divider 10 (LFAST) */
#endif

Slave lfast of clock settings:SIUL2.MSCR[135].R = 0x32000001; 

How to set the clock for master lfast???

Hope to answer,Thanks.

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petervlna
NXP Employee
NXP Employee

Hi,

As reference manual describes you have following possibilities:

The LFAST PLL requires a 20 MHz reference. The source may be the PLL0_PHI_CLK,PLL1_PHI_CLK, IRC_CLK, SDPLL_CLK, the external oscillator (XOSC_CLK) or input from the external LFAST device via PAD_135 package pin.

pastedImage_1.png

When this reference clock is generated internally, it can also be output on the PAD_135 pin. The PAD_135 connection is shown in Figure 5-7. Input/Output direction of PAD_135 pin is controlled by MSCR135 in the SIUL2.

So choose the one of the clock sources and set divider to output 20MHz.

regards,

Peter

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