How to config SPI CS pin of MPC574XB

[julieliu]

Hello this is the SPI cs  pin (MPC574XB) :

PJ[2]		146	0000_0000	GPIO[146]	SIUL2		I/O
PJ[2]			0000_0001	CS0_1	SPI_1		O
PJ[2]			0000_0010	CS0_2	SPI_2		O
PJ[2]			0000_0011	CS0_3	SPI_3		O
PJ[2]			0000_0100	SAI1_D0	SAI1		O
PJ[2]		-	-	ADC0_S[26]	ADC_0		I
PJ[2]		817	0000_0010	SS_1	SPI_1		I
PJ[2]		820	0000_0011	SS_2	SPI_2		I
PJ[2]		823	0000_0010	SS_3	SPI_3		I
PJ[2]		1010	0000_0001	SAI1_D0	SAI1		I

And I choose CS0_2 as the chip select  pin function but now I can not drive this pin to logical low.

here is my setting:

    /* Pad PJ2 souce signal is SPI_2 CS0_2 */
    FLASH_EXT_SIUL2_MSCR(146)      |= FLASH_EXT_SIUL2_MSCR_OBE_EN;      /* OEB=1 */
    FLASH_EXT_SIUL2_MSCR(146)      |= FLASH_EXT_SIUL2_MSCR_SSS_2;       /* Select function 2 */
    FLASH_EXT_SIUL2_MSCR(146)      |= FLASH_EXT_SIUL2_MSCR_SRC_3;       /*  Full slew rate  */

        /* CS ON (= LOW) */
        FLASH_EXT_SIUL2_GPDO_REG8(146)  &=FLASH_EXT_SIUL2_GPDO_LOW;         /* Logic low value */

Does anyone have any idea how to drive CS0_2 to low level.

[PetrS]

Hi Julie,

If you select SPI function on the pin (using SSS=2) then writing to GPDO register has no effect; the SPI2 module control the pin. If you want to control PJ[2] pin by SW then select GPIO functionality (SSS=0).

BR, Petr.

[julieliu]

Hello,

Thanks for your last reply.

But now I encounter another issue with CS.

I send commend 0x06 from Claypso though SPI to external flash called S25FL256SDPBHVC03.

I actally pull down the CS before send commend and pull up after I checked the commend is finished(SPI2_SR[TCF] ==1).

but the wave I captured show CS could not work well as following the CS pulled up earlier than needed:

Do you have any idea and what should be checked.

Thanks.

Julie

[PetrS]

Did you clear TCF before you send new command?

Anyway, why don't you simply use the SPI module to drive the CS signal? Set the pin for SPI2 CS0 function and once the PUSH register is going to be filled set the PCS0 bit in command word.

RB, Petr

[julieliu]

hello Petr,

I do follow you advice but there will be issue when I want to hold CS to low more than 8 bytes.

Now I configure push register with PCS to 1,but just after the CS will back to high.

but what I need is CS hold to low after I send instruction and  read data as following:

Do you have a way to hold the CS to low before I want it to high.

thanks a lot.

julie

[PetrS]

The Continuous Selection format can be used, read chapter 40.5.6.5 in the RM

Set the CONT bit in command (PUSHR) for (1 to n-1) bytes in the frame and clear CONT for last byte.

BR, Petr

[julieliu]

hello Petr,

Another question about the SPI pop register.

When I send a commend 0x9F to read external flash id.

Then I give a dummy data on push register to generate a 8 bit clock so I can read data.

I expect data to be 0x1 0x2 but what I read is 0 0x1 0x2.

the wave seems ok but the pop register seems one byte behind what I need.

So do you have any idea how to read correctly.

thanks.

julie

[julieliu]

hello Petr,

I add the picture to you :

First line is SOUT and at the second 8bit clock I received a 0x01on SIN  but only read out 0 from pop.

One point I don't understand is why there is a small high level on SOUT when I only send 0 on push register.

please have a look.

br,

julie

[julieliu]

hi Petr,

The issue seems with

POPNXTPTR field in SR register which says that:
Contains a pointer to the RX FIFO entry to be returned when the POPR is read. The POPNXTPTR is
updated when the POPR is read.

But on my side it will increa every time I write to the Push register.

In this case when I send a command it will increa and when I read pop it will not correct.

I want to know if there is a issue here.

br,

julie

[julieliu]

Hello ,

Thanks for your help and it really need to be so.

Br,

Julie