How to config CAN2 RXFIFO DMA on MPC5746C?

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How to config CAN2 RXFIFO DMA on MPC5746C?

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huocan
Contributor I

I try to  config CAN2 RXFIFO DMA,but it not work The follow is my Init code

/*************************DMA init**************************/

void CAN2_DMA_Init2(void)
{
DMAMUX_0.CHCFG[1].R = 0x80 | 5; //Route FlexCAN1 to DMA CHANNEL 0

DMA.TCD[1].SADDR.R = CAN2_BASE_ADDRESS + 0x80; /* Load Address of Source data */
DMA.TCD[1].ATTR.B.SSIZE = 2; /* Read 2**0 = 1 byte per transfer 32bit*/
DMA.TCD[1].ATTR.B.SMOD = 0; /* Source Modulo feature not used */
DMA.TCD[1].SOFF.R = 4; /* After tranfer, add 0 to src addr */
DMA.TCD[1].SLAST.R = -16; /* No address Adjustment after major loops */

DMA.TCD[1].DADDR.R = (unsigned int)&RxDATA1[0]; /* Destination Address */
DMA.TCD[1].ATTR.B.DSIZE = 2; /* Write 2**0 = 1 byte per transfer */
DMA.TCD[1].ATTR.B.DMOD = 0; /* Destination modulo feature not used */
DMA.TCD[1].DOFF.R = 4; /* Increment destination addr by 1 */
DMA.TCD[1].DLASTSGA.R = -16; /* No addr adjustment after major loop */

DMA.TCD[1].CSR.B.DREQ = 0; /* Don't Disable Request */
DMA.TCD[1].NBYTES.MLNO.B.NBYTES = 16; /* NBYTES - Transfer 1 byte per minor loop */
/* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
DMA.TCD[1].CITER.ELINKNO.B.ELINK = 0; /* Enable channel-to-channel linking on minor-loop complete */
DMA.TCD[1].CITER.ELINKNO.B.CITER = 1; /* Current Major Iteration Count */
/* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
DMA.TCD[1].BITER.ELINKNO.B.ELINK = 0; /* Enables channel-to-channel linking on minor loop complete */
DMA.TCD[1].BITER.ELINKNO.B.BITER = 1; /* Starting Major Iteration Count */
DMA.TCD[1].CSR.B.MAJORELINK = 0; /* Enable channel-to-channel linking on major loop complete */
DMA.TCD[1].CSR.B.ESG = 0; /* Enable Scatter/Gather Processing */
DMA.TCD[1].CSR.B.BWC = 0; /* Bandwidth Control */
DMA.TCD[1].CSR.B.INTHALF = 0; /* Disable an interrupt when major counter is half complete. */
DMA.TCD[1].CSR.B.INTMAJOR = 1; /* Disable an interrupt when major iteration count completes */
DMA.TCD[1].CSR.B.MAJORLINKCH = 0; /* Link Channel Number */
DMA.TCD[1].CSR.B.START = 0; /* Channel Start */
DMA.TCD[1].CSR.B.DONE = 0; /* Channel Done */
DMA.TCD[1].CSR.B.ACTIVE = 0; /* Channel Active */
INTC.PSR[70].B.PRC_SELN0 = 0x1; /* IRQ sent to Core 0 */
INTC.PSR[70].B.PRIN =10; /* IRQ priority = 10 (15 = highest) */

DMA.SERQ.R = 1; /* Enable channel 0 */
}

 

/***********Can2 init*******************/

void initCAN_2_rx(void) { /* General init. MB IDs: MB4 ID_STD=0x555 */
uint16_t i;

CAN_2.MCR.B.MDIS = 1; /* Disable module before selecting clock source*/
CAN_2.CTRL1.B.CLKsrc=0; /* Clock Source = oscillator clock (40 MHz) */
CAN_2.MCR.B.MDIS = 0; /* Enable module for config. (Sets FRZ, HALT)*/
while (!CAN_2.MCR.B.FRZACK) {}/* Wait for freeze acknowledge to set */
/* Good practice: wait for FRZACK on freeze mode entry/exit */

CAN_2.CBT.R = 0x802D29AD; // Nominal bit time: 40 MHz clksrc, 500K bps with 40 tq
// EPRESDIV = 1, EPROPSEG = 10, EPSEG1 = 13, EPREG2 = 13
CAN_2.CBT.B.EPRESDIV = 3;
CAN_2.FDCBT.R = 0x00130443; // Data bit time: 40 MHz clksrc, 2Mbps with 10 tq
// FPRESDIV = 1, FPROPSEG = 2, FPSEG1 = 3, FPREG2 = 4
for (i=0; i<64; i++) { /* MPC574xG has 96 buffers after MPC5748G rev 0*/
CAN_2.MB[i].CS.B.CODE = 0; /* Inactivate all message buffers */
}

CAN_2.RXFGMASK.R = 0x0;
for(i=0;i<64;i++)
{
CAN_2.RXIMR[i].R = 0x1FFFFFFF;
// CAN_2.RXIMR[i].R = 0x00000000;
}

SIUL2.MSCR[72].B.SSS = 1; /* Pad PB0: Source signal is CAN2_TX */
SIUL2.MSCR[72].B.OBE = 1; /* Pad PB0: Output Buffer Enable */
SIUL2.MSCR[72].B.src=3; /* Pad PB0: Maximum slew rate */
SIUL2.MSCR[73].B.IBE = 1; /* Pad PB1: Enable pad for input - CAN2_RX */
SIUL2.IMCR[190].B.SSS = 1; /* CAN2_RX: connected to pad PB1 */

 

CAN_2.CTRL2.B.RFFN = 0x0; /* Message buffers 0-7 are occupied by RX FIFO and ID filter table */
/* There are 8 ID filter table elements */

CAN_2.MCR.B.IDAM = 0x0; /* One full ID (standard and extended) per ID Filter Table element */

/* Enable DMA, enable RX FIFO, negate FlexCAN 0 halt state for 64 MBs */
CAN_2.MCR.R = 0x2000803F;
while (CAN_2.MCR.B.FRZACK & CAN_2.MCR.B.NOTRDY) {} /* Wait to clear */
/* Good practice: wait for FRZACK on freeze mode entry/exit */
}

 

void AIPS_Init(void)
{
/* Enable DMA access on Peripheral Bridges*/
AIPS_A.MPRA.B.MTR4 = 1;
AIPS_A.MPRA.B.MTW4 = 1;
AIPS_A.MPRA.B.MPL4 = 1;

AIPS_B.MPRA.B.MTR4 = 1;
AIPS_B.MPRA.B.MTW4 = 1;
AIPS_B.MPRA.B.MPL4 = 1;
}//AIPS_Init

/************************ISR****************************/

void DMA_17_ISR(void)
{
/* Received frame is available in array RxDATA */


DMA.INT.R = 0x00020000; /* Clear interrupt flag for DMA channel 0 */
}

int main()

{

peri_clock_gating();
Sys_Init();
SIUL2_Init ();

initCAN_2_rx();

CAN2_DMA_Init2();

 

while(1){

// TransmitMsg();
for(i = 0; i < 10000; i++)
{}
i = 0;
}

}

Is the DMA configuration channel of can2 correct ? Interrupt of DMA_17_ISR cannot be triggered

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