How to clean EIN_ERR (NCF 54) in FCCU of MPC5777Mv2

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How to clean EIN_ERR (NCF 54) in FCCU of MPC5777Mv2

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truongtran1
Contributor II

Hi folks,

I am working with FCCU feature of MPC5777M.

I always go the error of channel 54, in the Reference Manual, it is caused by external error, meaning some external devices were driving my ERROR pin.I am pretty sure that I used error pins as output of FCCU (refer to the simplified schematic, SIUL and FCCU configuration).

So my expectation that the FCCU shall be zero fault, could you please let me know how to clean it out?

I didn't found any errata related to this problem as well.

May you help me to identify what I am doing wrong here?

Best Regards,

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I think it works as you said.

Other devices having FCCU has either dedicated EOUT outputs and EIN inputs, or it does not have FCCU external inputs at all.

Here it is implemented differently, it uses EOUT as bi-directional I/Os what means it works simultaneously

“The FCCU provides up to two bidirectional signals (EOUT interface) as a failure indication to the external world. These signals need to be mapped to appropriate pins for external visibility. Since SIUL2 does not control the pad buffer enable during Alternate function, FCCU provides a mechanism to drive the pad in OD (Open Drain) mode where the pad is driven Hi-Z only when FCCU drives logic '1' else it drives logic '0' (when FCCU drives logic '0'). The selection to OD is done by OD bit in FCCU_CFG register.”

 

Due to that I suppose there is expected is either compounded function with open-drain where either ends may report faults over FI[0] pad. It means input buffers are always active even for output functionality with push-pull drivers. In my opinion it is just needed to ignore NCF54 (do not set any reaction) if you don’t use FI[0] pin as input.

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truongtran1
Contributor II

Thanks davidtosenovjan for your recommendation.

I saw the application note on connection between MPC5774P and MC33908 stated that "It is
necessary to use pull up (IO_3) and pull down (IO_2) resistors. The resistors define default state and
avoid wrong error detection during startup phase or other phase when MPC5744P does not drive these
pins."

This mean during startup, my EOUT[1:0] is 0b10, I assumed the SBC shall consider it is the NoFault state during startup, so 0b10 shall be NoFault and vice versa, 0b01 is Faulty state. and that mean the PS bit shall be set to "1" on both FCCU and SBC side, and I just ignore the NFC54 fault channel.

Is that make sense?

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I believe you may find the answer here:

https://community.nxp.com/thread/491392 

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truongtran1
Contributor II

Does anyone have any idea?

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truongtran1
Contributor II

Update, I though I found the problem. After changing the PS bit to 0 (EOUT1 active low, EOUT0 active high), the fault is cleared out accordingly.

It arises another concern to me that is that a normal operation. It seems the EOUT function and EIN function is mixed to one pin and the Error Input function is still working even I set that pin to be push-pull.

I am interested to see your comment.

Best Regards,

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