How to Trigger Data Storage Exception Due to Write Access Control When MSRPR=1

[Santhoshraj]

Hi,

According to the documentation, store operations such as dcba[e] and dcbz[e] are not permitted on certain memory pages when MSRPR=1.

When such an operation is attempted, it is expected to trigger a Data Storage Interrupt due to a Write Access Control Exception but it is not Triggering.

I want to know the exact steps to intentionally trigger this exception for testing and debugging purposes.

Processor: mpc5777c

Development Environment: adamutli

[davidtosenovjan]

Could you describe this test procedure more in detail?

[Santhoshraj]

Hi sir,

I have followed the test procedure as outlined and have attached the relevant screenshots for reference. Please review them still If you need a more detailed explanation, let me know 

Thank you!

[davidtosenovjan]

OK, these are screenshoots from manual. I wanted to see specific setup as you have.

[Santhoshraj]

Hi sir,

Code 

asm("lis r3,0×0402");

asm("ori r3,r3,0x1200");

asm("mtmsr r3");

asm("lis r3,0x0402");

asm("ori r3,r3,0x4000");

asm("mtspr ESR,r3");

[davidtosenovjan]

try to put synchronization instruction in between spr writes

[Santhoshraj]

Not working With synchronization instruction please suggest me any other solution

[davidtosenovjan]

What it does actually? Do you see other exception that expected or register is just accessed even in user mode? If you stepping the code in the debugger, does it behave same way?

[Santhoshraj]

I am trying different methods to trigger DSI

Code

uint16t value=0xFFFF;

uint32_t base_address=0x80000000;

*(uint16_t)base_address=value

For above code it have to trigger data storage exception but it is trigger data tlb exception 

Another method

Asm("lis r3,0×0000");

Asm("ori r3,r3,0×4000);

Asm("mtspr r3");

Asm("lis r3,0×0000");

Asm("ori r3,r3,0×003f);

Asm("mtmas3 r3");

As per manual I followed the steps it have to trigger data storage but it is Triggering program exception 

[davidtosenovjan]

I just tested it and I achieved Data Storage Interrupt (IVOR2) by MMU setting (in my configuration I have set user permission for NOT PERMITTED for EBI space i.e. 0x2000_0000), setting Problem State (PR) bit in the Machine State Register (MSR) to enable user mode and then attempting to write this address 0x2000_0000 and that’s it

Code triggering the exception:

e_lis  r30,0x0200

e_or2i r30,0xD000

mtmsr r30

e_lis r30,0x2000

e_or2i r30,0x0000

e_lis    r31,0xcafe

e_or2i   r31,0xbeef

e_stw   r31,0(r30)

MMU TLB2 init code changed changed following way:

#TLB2 = external bus @ 0x2000_0000, VLE

    e_lis   r3,0x1002

    mtspr   mas0,r3

    e_lis   r3,0xC000

    e_or2i  r3,0x0700

    mtspr   mas1,r3

    e_lis   r3,0x2000

    e_or2i  r3,0x0020

    mtspr   mas2,r3

    e_lis   r3,0x0000

    #e_or2i  r3,0x003F # user mode not permitted

    e_or2i  r3,0x0015

    mtspr   mas3,r3

    tlbwe