How to Enable I-CACHE & D-CACHE on MPC5674F

[youngseolee]

i try to eable i-cache and d-cache on MPC5674F, 

How to find out that cache is enabled? 

[davidtosenovjan · Accepted solution]

Hi, please pay attention to following example code:

Example XPC567XFKIT PinToggleStationery CW210 

If you open Optimizations.c file, you may see initialization of both caches.

Easiest way how to check it is enabled, is to see cache content (if your debugger allows it) if there is some content there:

[youngseolee]

Hi, I implemented the SRAM optimizations code as you told me, and the SRAM seems to be optimized.

And I'm measuring an access time of an external SSRAM using an internal PIT module on MPC5674F.

However, the measured access time of the external SSRAM differs depending on internal SRAM settings.

(The internal SRAM access time is the same.)

I used two versions of the code to measure time.

1. a code generated by using RAppID. (This code initializes the SRAM using the assembler.)

2. a code based on the example code you attached.

I think the SRAM initialization and optimization of both codes is the same, but in the first code, the following code for stack initialization has been added.

===================================================================

stack_inSRAM:

   e_lis            r1, __SP_INIT@h         ; Initialize stack pointer r1 to

   e_or2i          r1, __SP_INIT@l         ; value in linker command file.

         .

         .   

         .

      e_stwu      r1,-64(r1)                     ; terminate stack

===================================================================

I do not understand why the presence of this code affects the external RAM access time. (If I add the above part to the
code 2, exception handling interrupts occur continuously.)

Will the external SRAM access time be different because of the code attached above?

How to solve this problem?