How do to arrive the only core 0 can access Port X GPDO with MPC5746R SMPU

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How do to arrive the only core 0 can access Port X GPDO with MPC5746R SMPU

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Contributor I

I would like to use MPC5746R SMPU_1 to protect some SIUL(for example: Port X GPDO regsiters)

Core 0 can read/write Port X GPDO, but Core 1 can't read/write Port X GPDO.

Configuration 1:

(uint32_t)(&SIUL2.GPDO[IODRV_PX * IODRV_PORT_PIN_NUM]),                    //  SMPU_RGDn_WORD0
(uint32_t)(&SIUL2.GPDO[IODRV_PX * IODRV_PORT_PIN_NUM] + sizeof(SIUL2_GPDO_tag) * IODRV_PORT_PIN_NUM),                                                                                     //  SMPU_RGDn_WORD1 
SMPU_CORE0_MP_SHIFT(SMPU_RW) | SMPU_CORE1_MP_SHIFT(SMPU_NO) | SMPU_CORE0_DEBUG_MP_SHIFT(SMPU_RW),                                               //  SMPU_RGDn_WORD2 
SMPU_VLD                                                                                                             //  SMPU_RGDn_WORD3

If I enable SMPU_1, all registers will be protected except  Port X GPDO. So I add new configuration for all registers

Configuration 2:

0xF0000000,
0xFFFFFFFF,
SMPU_CORE0_MP_SHIFT(SMPU_RW) | SMPU_CORE1_MP_SHIFT(SMPU_RW)
| SMPU_CORE0_DEBUG_MP_SHIFT(SMPU_RW) | SMPU_CORE1_DEBUG_MP_SHIFT(SMPU_RW)
| SMPU_DMA0_MP_SHIFT(SMPU_RW),
SMPU_VLD

As result, Configuration 1 will lost function. How do to arrive the only core 0 can access Port X GPDO with MPC5746R SMPU?  

(In my application, some registers should be configured by core 0. we would like core 1 without any possible to modify core 0 registers. Also core 1 can access another ports like Port A GPDO, Port Z GPDO)

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NXP TechSupport
NXP TechSupport

Access to uncovered area leads to access violation. Once the SMPU is enabled, all used resources needs to be covered by descriptors.

Overlapping can be used (and is supposed to be used) in different way - you can use one descriptor to protect whole area of peripheral reigisters and then use other descriptors to allow access to certain locations. Depending on number of areas, this could save some descriptors.

Regards,

Lukas

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NXP TechSupport
NXP TechSupport

Hi Ricky,

this is mentioned in the reference manual:

"Priority given to granting permission over denying access for overlapping region descriptors."

This is what happened in your configuration. Search for 'overlap' keyword in SMPU chapter for more details.

Solution is: configure three descriptors. First one will cover area 0xF0000000 up to some GPDO register, second will cover GPDO register(s) and third will cover the rest of space up to 0xFFFFFFFF. So, the descriptors will not overlap.

Regards,

Lukas

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Contributor I

Hi Lukas,

Thanks, I  go it. 

It seems to bad to me, because I want to use SMPU to protect Port X, Port H, INTC (STM, eMISO, FCCU),  As your decription,  I will use 11 SMPU regions but SMPU_1 only have 8 regions.

In my mind, if I would like to protect some peripheral registers, I only to config those registers, otherwise, another registers can be access without any SMPU limit.

 

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NXP TechSupport
NXP TechSupport

Access to uncovered area leads to access violation. Once the SMPU is enabled, all used resources needs to be covered by descriptors.

Overlapping can be used (and is supposed to be used) in different way - you can use one descriptor to protect whole area of peripheral reigisters and then use other descriptors to allow access to certain locations. Depending on number of areas, this could save some descriptors.

Regards,

Lukas

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