How do I activate an CAN RX interrupt on an MPC5646C when the frame is available in FIFO?

[sandrine_labois]

Hello,

I have configured the MCR register as above :

        CAN_0.MCR.R = (0
                        | HAL_FLEXCAN_MCR_FRZ          /* enabled to enter Freeze mode */
                        | HAL_FLEXCAN_MCR_FEN          /* enabled Rx FIFO : replacing MB[0...7] */
                        | HAL_FLEXCAN_MCR_HALT         /* enter freeze mode if FRZ bit is set */
                        | HAL_FLEXCAN_MCR_SRXDIS    /* self reception disabled */
                        | HAL_FLEXCAN_MCR_IDAM_00    /* IDAM = 00 : One full ID (standard or extended) per filter element.*/
                        | 0x0000003F);                                  /* MAXMB : enable 64 MBs */

      CAN_0.RXFIFO.IDTABLE[0].R = (0x7DF << 1)

      CAN_0.RXFIFO.IDTABLE[1..7].R = 0x00000000

        /* ----------------------------------------------------------- */
        /*          RXGMASK global mask                             */
        /* ----------------------------------------------------------- */
        CAN_0.RXGMASK.R  = 0xFFFFFFFF;

        /* ----------------------------------------------------------- */
        /*         RX14MASK buffer 14 mask                       */
        /* ----------------------------------------------------------- */
        CAN_0.RX14MASK.R  = 0xFFFFFFFF;

        /* ----------------------------------------------------------- */
        /*         RX15MASK buffer 15 mask                       */
        /* ----------------------------------------------------------- */
        CAN_0.RX15MASK.R  = 0xFFFFFFFF;

At first, did I configure the MPC5646C correctly?

After, how do I activate an CAN RX interrupt when the frame is available in FIFO?

Thank you for your support

Sandrine

[PetrS]

Hi Sandrine,

Flags are set in following way when FIFO is enabled. The 8 least significant interrupt flags (BUF7I–BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used. In details

- BUF5I - Frames available in FIFO. Once set you should read the MB0

- BUF6I - FIFO Warning. 5 frames have accumulated in the FIFO.

- BUF7I - FIFO Overflow. The FIFO is full and subsequent frames are not accepted until the CPU creates space in the FIFO by reading one or more frames (using MB0 still !!!). While the FIFO is full, the frames are only received if they are matched with another MBs.

So to enable RX FIFO interrupt you need to set corresponding bit in the IMASK1 register…

CAN_0.IMASK1.R = 0x00000020;                // enable BUF05I interrupt

See attached code I tested on the TRK-MPC5606B board. It does communication between CAN1 and CAN0. CAN0 is used to receive the message and RXFIFO is enabled and ISR is called when message is received. You can reuse the code as FlexCAN modules are similar.

BR, Petr