How can i get the maximum STCU2 clock of MPC5777C?

[jongminna]

Dear NXP engineers,

I want to find out the maximum clock for the STCU2 of MPC5777C.

As you know, I have to write the UTEST area with DCF.

Even if I can overwrite DCF area for the STCU2, I have a limited chance for the STCU clock configuration.

Refer to MPC5777C_BIST_Execution_Time.xlsx which is attached to AN5288, On-line and Off-line test time is too long to meet our customer's requirement. So I think I have to change PLL configuration.

For this reason, I have 2 questions.

Plus, This is my system information.

1. XOSC : 40MHz X-tal.

2. System clock : 264MHz

3. Power-up delay according to our customer's requirement : under the 50ms

    Power-down delay according to our customer's requirement : under the 50ms

Question 1 : If you did test with maximum clock, same as shortest execution time of off-line and on-line test result, Please let me know that result.

Also We should test all memory and logic partition.

Question 2  : Do we have to set to 50MHz for the STCU2 if we want to stable operation?

According to the AN5288, MPC5777C STCU Quick Start Guide

I could see recommended register value. Like below.

Recommended Register Value
• SIU_SYSDIV: 0x0000B010

Recommended Register Value
• PLLDIG_PLL0DV: 0x2006200F

Both 2 case STCU clock is 50MHz, So I worried that If I would set to above 50MHz, There would be unexpected error during execution.

Our OEM doesn't want to unexpected execution and error.

Please give me your valuable answer!

[petervlna · Accepted solution]

Hello,

A1:

The STCU module is clocked from PBRIDGE clock. However if you are referring to max full BIST frequency, this is recommended as 50MHz running from PPL clock as it is described in AN5288. If you are running M-BIST only then you can go up to 200MHz. Actually the 50MHz clock for LBIST doesn't make it slower (due to dividers), but the MBIST is 4x longer. Solution which customers are using is to do offline MBIST only and then full LBIST later onlune when there is a time.

A2:

yes, this is the case.

The reason for 50MHz recommended frequency is LBIST on high frequency draw a lot of current in short time and can cause HVD/LVD assertion in some cases like process and temperature corner cases. So we can guarantee 50MHz here.

Peter

[jongminna]

Thanks for Peter!

Your answer is helpful.

Could you explain below sentence more specifically?

"Actually the 50MHz clock for LBIST doesn't make it slower (due to dividers), but the MBIST is 4x longer."

It means LBIST will run at 50MHz and MBIST run at 12.5MHz(50/4 = 12.5). Right?

Thanks again,

JM

[petervlna]

Hi,

No you didn't understand me.

It is no difference if you run LBIST on 200 or 50MHz.

But the MBIST on 50MHz is 4x slower then MBIST on 200MHz.

Peter

[jongminna]

Peter,

I have one more question. 

According to AN5288, 10page, I could see below sentence(I highlighted)

It means that even If I configure the on-line clock to 200MHz, LBIST will be running in 50MHz.

On the other hands, LBIST can be running up to 50MHz in the off-line and on-line also. Is it right?

[petervlna]

Hi,

It means if you configure on-line STCU clock for 200MHz, then BIST will run at 200MHz. (LBIST and MBIST)

I recommend you to run BIST at 50MHz to avoid any issues.

I personally do not agree with AN that you can run at 200MHz LBIST, as there is a lot of current draw during LBIST. I see no issue for MBIST at 200MHz. But if you need to do complete test then use 50MHz.

Peter