Hi lukaszadrapa,
thanks for your support !!
i got some updates for this link !
regarding your statement :
@the only thing which comes into my mind - do you use data cache? Have you tried to disable it for test purposes?
--> i said i have disabled data cache, but it was not working. (How did i disable cache? it is through MMU TLB settings for SRAM memory)
Now, i figured out some settings in MMU during Startup code.
I hope you're aware of TLB settings (i.e. we allocate/Map/reference physical memory as TLBs along with some memory settings and allow users/code to get access to memory).
For the above Global variable behaviour (in fact SRAM behavior) i have applied some MMU-TLB settings and tested. i figured out some test scenarios as below (of which some gave me desired output ):
SRAM - MMU TLB setting CASE 1 :
1. TLB number = 3 ,
2. TLB size = Entire SRAM (512KB),
3. Cache enabled [I bit not set i.e. Cache-Inhibition disabled ]
Status : Not working i.e. above garbage behaviour
SRAM - MMU TLB setting CASE 2 :
1. TLB number = 3 ,
2. TLB size = Entire SRAM (512KB),,
3. Cache Disabled[I bit set i.e. Cache-Inhibition enabled]
Status : Not working i.e. above garbage behaviour
SRAM - MMU TLB setting CASE 3 :
1. TLB number = 2 ,
2. TLB size = Entire SRAM (512KB),,
3. Cache Disabled[I bit set i.e. Cache-Inhibition enabled]
Status : Working , valid values observed on Variables and everything is fine
SRAM - MMU TLB setting CASE 4 :
1. TLB number = 2,3,4,5 (i.e. split SRAM to differnet TLBs) ,
2. each TLB size = 64KB,64KB ,64KB 256KB respectively
3. Cache Disabled[I bit set i.e. Cache-Inhibition enabled] for all TLBs or any one TLB (e.g : only TLB 3 and i map my global variables to this cache-inhibited TLB 3)
Status : Working , valid values observed on Variables and everything is fine
So, i have some questions from the above cases
Q1 : I think TLB numbers are irrespective of the Memory and work as per the start address and size, right? so why was data cache effective only after i allocate the SRAM to TLB 2 instead of TLB 3 ?? (comparing case 2 and 3)
Q2 : Also is it correct to set memory settings for entire SRAM (i.e. all address ranges with different slave port banks as mentioned in my first comment) and will those settings be effective i.e. actually gets reflected on memory?? (comparing case 2 and 4)
Thanks for the time !!!!
