I have one question for FlexCan Mailbox.as mentioned in user mannual,each CAN channel support 96 message buffers.
which can be configued as rx or tx.but if the message number is greater than 96,how can we deal with the messages?
yes, I try to test the FIFO for flexCan,the main scripts are as belows:
FLEXCAN_DRV_Init(INST_CANCOM1, &canCom1_State, &canCom1_InitConfig0);
but unfortunately, I can't receive CAN messages in recvBuff.is there anything wrong?Do you have any suggestion?
hope your answer,thank you.
I download the example,and check the code.I see the filter for FIFO is working.
but I have some questions:
1,there are two kinds of MASK,one is FLEXCAN_RX_MASK_INDIVIDUAL, the other one is FLEXCAN_RX_MASK_GLOBAL.what's the difference for these two mask(s)?
2,regarding the function FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, id_counter, 0xFFFFFFFF),is the id_counter message buffer ID or the application message ID?
3,if I want to banding one message buffer with several specific application messages,how did I configure it?
4,if I use fifo and message buffer multiplexing together as shown in example,if the fifo occupied message buffer 0-7,if I try to set rx individual mask,is the message buffer starting from message buffer 8?
1) this configure MCR[IRMQ] bit, this bit indicates whether Rx matching process will be based either on individual masking (RXIMRn) or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK.
2) it is RXIMR register number
3) The Accepance mask registers are used to filter incoming ID. ID ranges can be used if mask register is set desirably. There is bit2bit correspondence between received ID, mask and programmed MB ID (or RXFIFO ID filter elements). The mask says if corresponding incoming ID bit is compared with programmed ID bit.
If mask bit is cleared the incoming ID bit is not compared, it is don’t care. If mask bit is set, then there must be exact match between incoming ID bit and programmed ID bit. To receive a message into a MB/RXFIFO all relevant bits with mask bit set must be equal to programmed one.
4) yes, in this case available MBs start from MB8
thank you. One more question,if I use FLEXCAN_DRV_SetRxIndividualMask to configue each message buffer when fifo is not enabled,the mask is working.
as shown in FLEXCAN_DRV_SetRxIndividualMask,when fifo is enabled and message buffer index is greater than fifo element threshold,it will quit from freeze mode,and I can't set individul mask for some specific Mb.
In fact, I have the requirement to use both fifo and message Id MASK,in this case,how to deal with it?
here is the function for setting individual mask:
DEV_ASSERT(instance < CAN_INSTANCE_COUNT);
CAN_Type * base = g_flexcanBase[instance];
if ((mb_idx > FLEXCAN_GetMaxMsgBuffNum(base)) || (mb_idx >= CAN_RXIMR_COUNT))
if (false == FLEXCAN_IsRxFifoEnabled(base))
if (id_type == FLEXCAN_MSG_ID_STD)
/* Set standard individual mask*/
FLEXCAN_SetRxIndividualStdMask(base, mb_idx, mask);
else if (id_type == FLEXCAN_MSG_ID_EXT)
/* Set extended individual mask*/
FLEXCAN_SetRxIndividualExtMask(base, mb_idx, mask);
/* Should not get here */
if (mb_idx > FLEXCAN_GetNoOfIndividualMBsRxFIFO(base))
/* In FIFO Mode get the Id Filter Format already configured by FLEXCAN_DRV_ConfigRxFifo */
formatType = FLEXCAN_GetRxFifoIdFormat(base);
FLEXCAN_GetRxFifoMask(id_type, formatType, mask));
I see no issue in the latest SDK 3.0.2
Using FIFO+DMA, since the FIFO depth is 6, in SDK,is there any funcion which can read out the buffer message at the same time?
in SDK,I use this function FLEXCAN_DRV_RxFifo(INST_CANCOM7,&recvBuff6),it could only read out one message each time.